Resets

5.3 External Reset (RESET)

The RESET pin is one of the two external sources of a reset. This pin is connected to a Schmitt trigger input gate to provide an upper and lower threshold voltage separated by a minimum amount of hysteresis. This external reset occurs whenever the RESET pin is pulled below the lower threshold and remains in reset until the RESET pin rises above the upper threshold. This active-low input will generate the RST signal and reset the CPU and peripherals. Termination of the external RESET input or the internal COP watchdog reset are the only reset sources that can alter the operating mode of the MCU.

NOTE: Activation of the RST signal is generally referred to as reset of the device, unless otherwise specified.

IRQ

 

 

 

TO IRQ

 

 

 

LOGIC

 

 

 

 

 

 

D

 

MODE

 

 

LATCH

 

 

 

 

SELECT

RESET

 

 

 

 

 

 

 

 

 

R

 

 

 

 

CLOCKED

 

 

OSC

COP WATCHDOG

 

 

 

DATA

 

 

 

(COPR)

 

 

 

ADDRESS

 

 

 

 

 

 

 

LPRST

 

 

CPU

 

 

 

 

 

 

 

S

 

 

 

POWER-ON RESET

D

 

TO OTHER

VDD

LATCH

 

 

PERIPHERALS

(POR)

RST

 

 

 

 

ILLEGAL ADDRESS

PH2

 

 

ADDRESS

 

 

 

(ILLADDR)

 

 

 

 

 

 

 

Figure 5-1. Reset Block Diagram

General Release Specification

 

MC68HC05RC16 — Rev. 3.0

 

 

 

46

Resets

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