Instruction Set
Instruction Set Summary
Table
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| Effect on | Address Mode | Opcode | Operand | Cycles | ||||
Source | Operation |
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| CCR |
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| H | I | N | Z | C |
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BIH rel | Branch if IRQ Pin High |
| PC ← (PC) + 2 + rel ? IRQ = 1 | — | — | — | — | — | REL | 2F | rr | 3 |
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BIL rel | Branch if IRQ Pin Low |
| PC ← (PC) + 2 + rel ? IRQ = 0 | — | — | — | — | — | REL | 2E | rr | 3 |
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BIT #opr |
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| IMM | A5 | ii | 2 |
BIT opr |
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| DIR | B5 | dd | 3 |
BIT opr | Bit Test Accumulator with Memory Byte |
| (A) ∧ (M) | — | — | ↕ | ↕ | — | EXT | C5 | hh ll | 4 |
BIT opr,X |
| IX2 | D5 | ee ff | 5 | |||||||
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BIT opr,X |
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| IX1 | E5 | ff | 4 |
BIT ,X |
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| IX | F5 |
| 3 |
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BLO rel | Branch if Lower (Same as BCS) |
| PC ← (PC) + 2 + rel ? C = 1 | — | — | — | — | — | REL | 25 | rr | 3 |
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BLS rel | Branch if Lower or Same |
| PC ← (PC) + 2 + rel ? C ∨ Z = 1 | — | — | — | — | — | REL | 23 | rr | 3 |
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BMC rel | Branch if Interrupt Mask Clear |
| PC ← (PC) + 2 + rel ? I = 0 | — | — | — | — | — | REL | 2C | rr | 3 |
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BMI rel | Branch if Minus |
| PC ← (PC) + 2 + rel ? N = 1 | — | — | — | — | — | REL | 2B | rr | 3 |
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BMS rel | Branch if Interrupt Mask Set |
| PC ← (PC) + 2 + rel ? I = 1 | — | — | — | — | — | REL | 2D | rr | 3 |
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BNE rel | Branch if Not Equal |
| PC ← (PC) + 2 + rel ? Z = 0 | — | — | — | — | — | REL | 26 | rr | 3 |
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BPL rel | Branch if Plus |
| PC ← (PC) + 2 + rel ? N = 0 | — | — | — | — | — | REL | 2A | rr | 3 |
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BRA rel | Branch Always |
| PC ← (PC) + 2 + rel ? 1 = 1 | — | — | — | — | — | REL | 20 | rr | 3 |
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| DIR (b0) | 01 | dd rr | 5 |
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| DIR (b1) | 03 | dd rr | 5 |
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| DIR (b2) | 05 | dd rr | 5 |
BRCLR n opr rel | Branch if Bit n Clear |
| PC ← (PC) + 2 + rel ? Mn = 0 | — | — | — | — | ↕ | DIR (b3) | 07 | dd rr | 5 |
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| DIR (b4) | 09 | dd rr | 5 |
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| DIR (b5) | 0B | dd rr | 5 |
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| DIR (b6) | 0D | dd rr | 5 |
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| DIR (b7) | 0F | dd rr | 5 |
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BRN rel | Branch Never |
| PC ← (PC) + 2 + rel ? 1 = 0 | — | — | — | — | — | REL | 21 | rr | 3 |
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| DIR (b0) | 00 | dd rr | 5 |
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| DIR (b1) | 02 | dd rr | 5 |
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| DIR (b2) | 04 | dd rr | 5 |
BRSET n opr rel | Branch if Bit n Set |
| PC ← (PC) + 2 + rel ? Mn = 1 | — | — | — | — | ↕ | DIR (b3) | 06 | dd rr | 5 |
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| DIR (b4) | 08 | dd rr | 5 |
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| DIR (b5) | 0A | dd rr | 5 |
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| DIR (b6) | 0C | dd rr | 5 |
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| DIR (b7) | 0E | dd rr | 5 |
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| DIR (b0) | 10 | dd | 5 |
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| DIR (b1) | 12 | dd | 5 |
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| DIR (b2) | 14 | dd | 5 |
BSET n opr | Set Bit n |
| Mn ← 1 | — | — | — | — | — | DIR (b3) | 16 | dd | 5 |
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| DIR (b4) | 18 | dd | 5 |
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| DIR (b5) | 1A | dd | 5 |
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| DIR (b6) | 1C | dd | 5 |
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| DIR (b7) | 1E | dd | 5 |
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| PC ← (PC) + 2; push (PCL) |
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BSR rel | Branch to Subroutine |
| SP ← (SP) – 1; push (PCH) | — | — | — | — | — | REL | AD | rr | 6 |
| SP ← (SP) – 1 | |||||||||||
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| PC ← (PC) + rel |
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CLC | Clear Carry Bit |
| C ← 0 | — | — | — | — | 0 | INH | 98 |
| 2 |
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CLI | Clear Interrupt Mask |
| I ← 0 | — | 0 | — | — | — | INH | 9A |
| 2 |
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MC68HC05RC16 — Rev. 3.0 |
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| General Release Specification | ||||||||
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MOTOROLA |
| Instruction Set |
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| 97 | |