Motorola MC68VZ328 7.3 Programming Model

7-12 MC68VZ328 User’s Manual 
Programming Model
7.3 Programming Model
This section describes the programming model for the DRAM controller.
7.3.1 DRAM Memory Configuration Register
The DRAM memory configuration register (DRAMMC) is used to set the DRAM refresh interval and
configure the address multiplexer for the specific memory device being used. The bit position and values
are shown in the following register displ ay. The details about the register settings are described in
Table 7-6.
DRAMMC DRAM Memory Configuration Register 0x(FF)FFFC00
BIT
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BIT 0
ROW12 ROW0 ROW
11 ROW 10 ROW 9ROW 8COL 10 COL 9COL 8REF
TYPE rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
RESET 0000 0 0 0 0 0 0 0 00000
0x0000
Table 7-6. DRAM Memory Configuration Register Description
Name Description Setting
ROW12
Bits 15–14 Row Address MD12—This field selects the row address bit for multiplexed address MD12. 00 = PA10 01 = PA21
10 = PA23
11 = Not valid
ROW0
Bits 13–12 Row Address MD0—This field selects the row address bit for multiplexed address MD0. 00 = PA11 01 = PA22
10 = PA23
11 = Not valid
ROW11
Bit 11 Row Address MD11—This bit selects the row address bit for multiplexed address MD11. 0 = PA20 1 = PA22
ROW10
Bit 10 Row Address MD10—This bit selects the row address bit for multiplexed address MD10. 0 = PA19 1 = PA21
ROW9
Bit 9 Row Address MD9—This bit selects the r ow address bit for multiplexed address MD9. 0 = PA9 1 = PA19
ROW8
Bit 8 Row Address MD8—This bit selects the r ow address bit for multiplexed address MD8. 0 = PA10 1 = PA20
COL10
Bit 7 Column Address MD10—This bit selects the column address bit for multiplexed address MD10. 0 = PA11 1 = PA0
COL9
Bit 6 Column Address MD9—This bit selects the column address bit for multiplexed address MD9. 0 = PA10 1 = PA0
COL8
Bit 5 Column Address MD8—This bit selects the column address bit for multiplexed address MD8. 0 = PA9 1 = PA0