15-2 MC68VZ328 User’s Manual
PWM 1

15.1.1 PWM Clock Signals

Figure 15-2 shows a simplified block diagram of PWM 1. The prescaler and divider generate the PCLK
signal from one of two clock signals—SYSCLK (the default) or CLK32. Selection of the source clock
used by the pulse width modulator is made by the clock source (CLKSRC) bit in the PWM 1 control
register.
The CLKSEL (clock selection) field in the PWMC1 selects the frequency of the output of the divider
chain. The incoming clock source is divided by a binary value between 2 and 16.
For 16 kHz audio applications, CLKSEL is equal to %01, divide by 4. For DC-level applications,
CLKSEL is equal to %11, divide by 16. In both cases, the following assumptions apply:
• SYSCLK = 16.58 MHz
• Prescaler = 0
• Period = default value
The 7-bit prescaler may be adjusted to achieve lower sampling rates by programming the prescaler field in
the PWM 1 control register with any number between 0 and 127, which scales down the incoming clock
source by a factor from 1 to 128, respectively.
15.2 PWM 1
PWM 1 is an 8-bit PWM module that is optimized to generate high-quality sound from stored sample
audio files. It can also generate simple or complex tones. It uses 8-bit resolution and a 5-byte FIFO to
generate sound. Figure15-2 illustrates the block diagram of the pulse-width modulator unit 1.
Figure 15-2. PWM 1 Block Diagram
Sample Compare PWMO
Output
Control
Prescaler Counter
SYSCLK
5-Byte FIFO
MPU Interface
Divider
CLK32
Period
CLKSRC
PCLK