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Motorola MVME177 manual General Description, FCC Compliance

Models: MVME177

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General Description

FCC Compliance

The MVME177 was tested in an FCC-compliant chassis, and meets the requirements for Class A equipment. FCC compliance was achieved under the following conditions:

1.Shielded cables on all external I/O ports.

2.Cable shields connected to earth ground via metal shell connectors bonded to a conductive module front panel.

3.Conductive chassis rails connected to earth ground. This provides the path for connecting shields to earth ground.

4.Front panel screws properly tightened.

For minimum RF emissions, it is essential that the conditions above be implemented; failure to do so could compromise the FCC compliance of the equipment containing the module.

General Description

The MVME177 is a double-high VMEmodule based on the

MC68060 microprocessor. The MVME177 has:

❏4/8/16/32/64/128/256 MB of ECC-protected DRAM

❏8KB of static RAM and time of day clock (with battery backup)

❏Ethernet transceiver interface

❏Four serial ports with EIA-232-D interface

❏Four tick timers

❏Watchdog timer

❏4 MB of Flash memory

❏Two EPROM sockets

❏SCSI bus interface with DMA

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Motorola MVME177 manual General Description, FCC Compliance

Contents

MVME177 Single Board Computer Installation and Use ManualRestricted Rights Legend Preface Page Adjusting This equipment. Use extreme caution when handling, testingPage Contents Page Page Flash Fill Test B-48Flash Patterns Test B-49 List of Figures List of Tables Model Designations IntroductionMVME177 Model Designations Model Number Speed Major DifferencesFeature Description FeaturesMVME177 Features Cooling Requirements SpeciﬁcationsMVME177 Speciﬁcations Characteristics SpeciÞcationsFCC Compliance General DescriptionMVME712AM Bbram MVME712M MVME712A MVME712AM MVME712B Equipment RequiredSystem V/68 Related DocumentationDocument Title Number MotorolaSupport Information Manual Terminology Unpacking Instructions Hardware Preparation and InstallationWhat you will need to do Refer to Overview of Start-up ProcedureStart-up Overview You may also wish to obtain AppearsInitialize the clock Examine and/or changeHardware Preparation MVME177 Switches, Headers, Connectors, Polyswitches LEDs Header Number Description ConÞguration Jumpers Conﬁguring MVME177 Headers1MB Eprom MVME177 Header Notes Header Number Description ConÞgurationDo not remove all jumpers from J2. This may Disable the Sram Setup Instructions Bit J1 Pins Description MVME177 Module Installation Instructions MVME177 Module Installation Instructions Hardware Preparation and Installation System Considerations Hardware Preparation and Installation MVME177 Module Installation Instructions Hardware Preparation and Installation Abort Switch S1 Controls and IndicatorsReset Switch S2 Front Panel Indicators DS1 DS4 Normal Address Range Memory MapsLocal Bus Memory Map Software Address Range Devices Accessed Port Size InhibitLocal Bus Memory Map Local I/O Devices Memory Map Address Range Devices Accessed Port Size$FFF77000 $FFF77FFF Reserved Multi-MPU Programming Considerations Local Reset OperationSoftware Initialization Sysreset Operating Instructions Data Bus Structure Functional Description IntroductionMVME177 Functional Description MPU Scsi BlockFlash Memory MC68060 MPUFlash Memory and Eprom Jumper or Control Bit Control Condition Memory ConÞguration Eprom and Flash Control and ConﬁgurationEprom Sram Do not short circuit Onboard Dram Battery Backed Up RAM and Clock Interfaces VMEbus InterfaceRXD CTS DCD TXD RTS DTR Serial Port InterfaceTXD RTS DTR Parallel Port Interface Ethernet Interface Scsi Termination Local ResourcesScsi Interface Software-Programmable Hardware Interrupts Programmable Tick TimersWatchdog Timer Timing Performance Module IdentiﬁcationLocal Bus Time-out Local Bus to Dram Cycle TimesScsi Transfers ROM Cycle TimesLAN DMA Transfers Remote Status and ControlAEIA-232-D Interconnections Table A-1. EIA-232-D Interconnections Pin Signal Number Mnemonic Signal Name and DescriptionPin Number Mnemonic Signal Name and DescriptionLevels of Implementation Sample Conﬁgurations Signal AdaptationsFigure A-1. Middle-of-the-Road EIA-232-D Conﬁguration Figure A-2. Minimum EIA-232-D Connection Proper Grounding EIA-232-D Interconnections Description of 177Bug Overview of M68000 FirmwareDebugger General Information 177Bug Implementation AutobootAutoboot in progress... To abort hit Break ROMboot Network Boot Restarting the System Abort ResetBreak MPU Clock Speed Calculation SYSFAIL* Assertion/NegationMemory Requirements Terminal Input/Output Control Blocks Versus Sectors Disk I/O SupportDebugger General Information IOC IOP IOT MAR MAW Device Probe FunctionIOP Physical I/O to Disk Disk I/O via 177Bug Commands IOI Input/Output InquiryBH Bootstrap and Halt BO Bootstrap Operating SystemIOT I/O Teach IOC I/O ControlDskcfig Network I/O Support Default 177Bug Controller and Device ParametersDisk I/O Error Codes UDP/IP Protocol Modules Intel 82596 LAN Coprocessor Ethernet DriverTftp Protocol Module Bootp Protocol ModuleRARP/ARP Protocol Modules Network I/O Error Codes Network Boot Control ModuleMultiprocessor Support Multiprocessor Control Register Mpcr MethodStatus codes that may be set by the bus master are Gcsr Method Diagnostic Facilities Test Group Description Table B-1. Diagnostic Test GroupsEntering Debugger Command Lines Using the 177Bug DebuggerBoldface strings Syntactic VariablesData Type Base IdentiÞer Examples Expression as a ParameterExpression Result In Hex String Numeric Value LiteralTable B-2. Debugger Address Parameter Formats Address as a ParameterAddress Formats Offset Registers 177BugMD 1327CDI Port Numbers IOP Entering and Debugging Programs177Bug Vector Table and Workspace Exception Vectors Used by 177Bug Hardware FunctionsVector Offset Exception 177Bug Facility Table B-3. Exception Vectors Used by 177BugUsing 177Bug Target Vector Table Creating a New Vector Table Except SUBQ.L 177Bug Generalized Exception Handler 177BugMD A7&30 Floating Point Data Types Floating Point SupportInteger Data Types This format would appear in memory as Single Precision RealPacked Decimal Real Double Precision RealExtended Precision Real Scientiﬁc Notation Additions to Flash CommandsErase Test Flash Test Conﬁguration Acceptable EntriesFlash Fill Test Diagflash eraseDiagflash fill Flash Patterns TestFigure B-1. Three Possible Mapping Options Default Flash Test ConﬁgurationSflash Command Sflashl Pflash ff800000 ff9fffff ffa00000 177Bug Debugger Command Set Command Command Line Mnemonic Title Syntax Table B-4. Debugger CommandsBI Range B W L Cnfg I MIOI CL ENV DR n a Niot H aPA n Nopa nVER E Or SET nCDebugger General Information First Second Controller Type Disk/Tape Controller Modules SupportedController Address Device Disk/Tape Controller Default ConﬁgurationsDevice Type Controller DeviceController MVME323 -- Four DevicesController LUN Address Device LUN Device Type MVME328 -- Fourteen DevicesFloppy Types and Formats IOT Parameter IOT Command Parameters for Supported Floppy TypesOther Conﬁgure Board Information Block CommandsConfigure and Environment Commands ENV D Set Environment to Bug/Operating System= EFFFFFFF? Master Starting Address #2 = 00000000? ENV Parameter and Options Default Meaning of Default Table D-1. ENV Command ParametersLUN Network Auto Boot Memory Search Starting Address $02 refer to the Memory Requirements Accessible by the VMEbus. Default is Slave Ending Address #2 Master Ending Address #3 Short I/O VMEbus A16 Control Network Controller Modules Supported ENetwork Controller DataClun Dlun Controller Interface TypeCondition Possible Problem Try This Table F-1. Basic Troubleshooting StepsCTRL-Q Envd CR Set mmddyyhhmm CRDe CR Env CRSt CR Index Index IN-7 IN-8 IN-9 IN-10 XON/XOFF