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Motorola MVME177 manual MC68060 MPU, Flash Memory and Eprom

Models: MVME177

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Functional Description

MC68060 MPU

The MC68060 microprocessor is the main processor for the

MVME177. The superscalar MC68060 processor has:

❏Two MC68040-compatible CPU integer cores

❏MC68040-compatible floating point core

❏Independent 8KB instruction and operand data caches

❏MC68040-compatible paged memory management unit

❏A bus controller

The processor is in a PGA socket. Its clock speed is 50 MHz (for the -00xmodels), and 60 MHz (for the -01xmodels). Note that the local processor bus runs at only half the processor speed. Refer to the MC68060 user's manual for more information.

Flash Memory and EPROM

Flash Memory

The MVME177 includes four 28F008SA Flash memory devices. The Flash devices provide 4MB of ROM at address $FF800000- $FFBFFFFF. The Flash is organized as one 32-bit bank for 32-bit code execution from the processor. The Flash could, for instance, be used for the onboard debugger firmware (177Bug) which would be downloaded from I/O resources such as:

❏Ethernet

❏SCSI

❏A serial port, or

❏The VMEbus

When Flash is used with EPROM, either the top or bottom 2MB of Flash is available in the second 2MB of memory space after the EPROM. Refer to Table 4-1 below.

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Motorola MVME177 manual MC68060 MPU, Flash Memory and Eprom

Contents

Single Board Computer Installation and Use Manual MVME177Restricted Rights Legend Preface Page This equipment. Use extreme caution when handling, testing AdjustingPage Contents Page Page Flash Fill Test B-48Flash Patterns Test B-49 List of Figures List of Tables Introduction Model DesignationsMVME177 Model Designations Model Number Speed Major DifferencesFeature Description FeaturesMVME177 Features Speciﬁcations Cooling RequirementsCharacteristics SpeciÞcations MVME177 SpeciﬁcationsGeneral Description FCC ComplianceMVME712AM Bbram Equipment Required MVME712M MVME712A MVME712AM MVME712BRelated Documentation System V/68Motorola Document Title NumberSupport Information Manual Terminology Hardware Preparation and Installation Unpacking InstructionsWhat you will need to do Refer to Overview of Start-up ProcedureStart-up Overview Appears You may also wish to obtainInitialize the clock Examine and/or changeHardware Preparation MVME177 Switches, Headers, Connectors, Polyswitches LEDs Conﬁguring MVME177 Headers Header Number Description ConÞguration Jumpers1MB Eprom Header Number Description ConÞguration MVME177 Header NotesDo not remove all jumpers from J2. This may Disable the Sram Setup Instructions Bit J1 Pins Description MVME177 Module Installation Instructions MVME177 Module Installation Instructions Hardware Preparation and Installation System Considerations Hardware Preparation and Installation MVME177 Module Installation Instructions Hardware Preparation and Installation Controls and Indicators Abort Switch S1Reset Switch S2 Front Panel Indicators DS1 DS4 Normal Address Range Memory MapsLocal Bus Memory Map Software Address Range Devices Accessed Port Size InhibitLocal Bus Memory Map Address Range Devices Accessed Port Size Local I/O Devices Memory Map$FFF77000 $FFF77FFF Reserved Multi-MPU Programming Considerations Local Reset OperationSoftware Initialization Sysreset Operating Instructions Data Bus Structure Functional Description IntroductionMVME177 Functional Description MPU Block ScsiFlash Memory MC68060 MPUFlash Memory and Eprom Eprom and Flash Control and Conﬁguration Jumper or Control Bit Control Condition Memory ConÞgurationEprom Sram Do not short circuit Onboard Dram Battery Backed Up RAM and Clock VMEbus Interface InterfacesSerial Port Interface RXD CTS DCD TXD RTS DTRTXD RTS DTR Parallel Port Interface Ethernet Interface Scsi Termination Local ResourcesScsi Interface Software-Programmable Hardware Interrupts Programmable Tick TimersWatchdog Timer Module Identiﬁcation Timing PerformanceLocal Bus Time-out Local Bus to Dram Cycle TimesROM Cycle Times Scsi TransfersRemote Status and Control LAN DMA TransfersAEIA-232-D Interconnections Pin Signal Number Mnemonic Signal Name and Description Table A-1. EIA-232-D InterconnectionsPin Number Mnemonic Signal Name and DescriptionLevels of Implementation Signal Adaptations Sample ConﬁgurationsFigure A-1. Middle-of-the-Road EIA-232-D Conﬁguration Figure A-2. Minimum EIA-232-D Connection Proper Grounding EIA-232-D Interconnections Overview of M68000 Firmware Description of 177BugDebugger General Information Autoboot 177Bug ImplementationAutoboot in progress... To abort hit Break ROMboot Network Boot Restarting the System Reset AbortBreak SYSFAIL* Assertion/Negation MPU Clock Speed CalculationMemory Requirements Terminal Input/Output Control Disk I/O Support Blocks Versus SectorsDebugger General Information Device Probe Function IOC IOP IOT MAR MAWDisk I/O via 177Bug Commands IOI Input/Output Inquiry IOP Physical I/O to DiskBO Bootstrap Operating System BH Bootstrap and HaltIOT I/O Teach IOC I/O ControlDskcfig Network I/O Support Default 177Bug Controller and Device ParametersDisk I/O Error Codes Intel 82596 LAN Coprocessor Ethernet Driver UDP/IP Protocol ModulesTftp Protocol Module Bootp Protocol ModuleRARP/ARP Protocol Modules Network Boot Control Module Network I/O Error CodesMultiprocessor Support Multiprocessor Control Register Mpcr MethodStatus codes that may be set by the bus master are Gcsr Method Diagnostic Facilities Table B-1. Diagnostic Test Groups Test Group DescriptionUsing the 177Bug Debugger Entering Debugger Command LinesSyntactic Variables Boldface stringsExpression as a Parameter Data Type Base IdentiÞer ExamplesString Numeric Value Literal Expression Result In HexTable B-2. Debugger Address Parameter Formats Address as a ParameterAddress Formats Offset Registers 177BugMD 1327CDI Port Numbers Entering and Debugging Programs IOP177Bug Vector Table and Workspace Hardware Functions Exception Vectors Used by 177BugTable B-3. Exception Vectors Used by 177Bug Vector Offset Exception 177Bug FacilityUsing 177Bug Target Vector Table Creating a New Vector Table Except SUBQ.L 177Bug Generalized Exception Handler 177BugMD A7&30 Floating Point Data Types Floating Point SupportInteger Data Types Single Precision Real This format would appear in memory asPacked Decimal Real Double Precision RealExtended Precision Real Additions to Flash Commands Scientiﬁc NotationFlash Test Conﬁguration Acceptable Entries Erase TestFlash Fill Test Diagflash eraseFlash Patterns Test Diagflash fillDefault Flash Test Conﬁguration Figure B-1. Three Possible Mapping OptionsSflash Command Sflashl Pflash ff800000 ff9fffff ffa00000 177Bug Debugger Command Set Table B-4. Debugger Commands Command Command Line Mnemonic Title SyntaxBI Range B W L Cnfg I MENV D IOI CLNiot H a R n aPA n Nopa nOr SET nC VER EDebugger General Information Disk/Tape Controller Modules Supported First Second Controller TypeDisk/Tape Controller Default Conﬁgurations Controller Address DeviceDevice Type Controller DeviceMVME323 -- Four Devices ControllerMVME328 -- Fourteen Devices Controller LUN Address Device LUN Device TypeIOT Command Parameters for Supported Floppy Types Floppy Types and Formats IOT ParameterOther Commands Conﬁgure Board Information BlockConfigure and Environment Commands Set Environment to Bug/Operating System ENV D= EFFFFFFF? Master Starting Address #2 = 00000000? Table D-1. ENV Command Parameters ENV Parameter and Options Default Meaning of DefaultLUN Network Auto Boot Memory Search Starting Address $02 refer to the Memory Requirements Accessible by the VMEbus. Default is Slave Ending Address #2 Master Ending Address #3 Short I/O VMEbus A16 Control ENetwork Controller Data Network Controller Modules SupportedController Interface Type Clun DlunTable F-1. Basic Troubleshooting Steps Condition Possible Problem Try ThisCTRL-Q Set mmddyyhhmm CR Envd CRDe CR Env CRSt CR Index Index IN-7 IN-8 IN-9 IN-10 XON/XOFF