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Motorola MVME177 manual Block, Scsi

Models: MVME177

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	VMEbus		Ethernet	SCSI		4 Asynchronous or
	A32/24:D64/32/16/08		Transceiver	Peripherals		3 Async/1 Sync
	Master/Slave
Figure	VMEbus		Ethernet	SCSI		Quad Serial	Port
	VMEchip 2	EPROM	i82596CA	53C710		CD2401	Parallel I/O
		EPROM
4	interface	2 44-pin PLCC	Controller	Coprocessor		I/O Controller	Centronics
4	interface		Controller	Coprocessor		I/O Controller	Centronics
-1.
MVME177							PCC2
							PCC2
							ASIC
Block	128KB	MC68060
	SRAM w/	MPU	4MB FLASH	Address	Data	Control	DS1643 or
	battery option	50 or 60 MHZ		Address	Data	Control	DS1643 or
Diagram	battery option	50 or 60 MHZ		MUX	MUX		MK48T08
Diagram						Battery Backed
						Battery Backed
						8KB RAM/Clock
				4 to 256MB ECC DRAM
							1818 9604

MVME177 Functional Description

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Motorola MVME177 manual Block, Scsi

Contents

MVME177 Single Board Computer Installation and Use ManualRestricted Rights Legend Preface Page Adjusting This equipment. Use extreme caution when handling, testingPage Contents Page Page Flash Fill Test B-48Flash Patterns Test B-49 List of Figures List of Tables Model Number Speed Major Differences IntroductionModel Designations MVME177 Model DesignationsMVME177 Features FeaturesFeature Description Cooling Requirements SpeciﬁcationsMVME177 Speciﬁcations Characteristics SpeciÞcationsFCC Compliance General DescriptionMVME712AM Bbram MVME712M MVME712A MVME712AM MVME712B Equipment RequiredSystem V/68 Related DocumentationDocument Title Number MotorolaSupport Information Manual Terminology Unpacking Instructions Hardware Preparation and InstallationStart-up Overview Overview of Start-up ProcedureWhat you will need to do Refer to Examine and/or change AppearsYou may also wish to obtain Initialize the clockHardware Preparation MVME177 Switches, Headers, Connectors, Polyswitches LEDs Header Number Description ConÞguration Jumpers Conﬁguring MVME177 Headers1MB Eprom MVME177 Header Notes Header Number Description ConÞgurationDo not remove all jumpers from J2. This may Disable the Sram Setup Instructions Bit J1 Pins Description MVME177 Module Installation Instructions MVME177 Module Installation Instructions Hardware Preparation and Installation System Considerations Hardware Preparation and Installation MVME177 Module Installation Instructions Hardware Preparation and Installation Abort Switch S1 Controls and IndicatorsReset Switch S2 Front Panel Indicators DS1 DS4 Local Bus Memory Map Memory MapsNormal Address Range Local Bus Memory Map Range Devices Accessed Port Size InhibitSoftware Address Local I/O Devices Memory Map Address Range Devices Accessed Port Size$FFF77000 $FFF77FFF Reserved Software Initialization Local Reset OperationMulti-MPU Programming Considerations Sysreset Operating Instructions MVME177 Functional Description Functional Description IntroductionData Bus Structure MPU Scsi BlockFlash Memory and Eprom MC68060 MPUFlash Memory Jumper or Control Bit Control Condition Memory ConÞguration Eprom and Flash Control and ConﬁgurationEprom Sram Do not short circuit Onboard Dram Battery Backed Up RAM and Clock Interfaces VMEbus InterfaceRXD CTS DCD TXD RTS DTR Serial Port InterfaceTXD RTS DTR Parallel Port Interface Ethernet Interface Scsi Interface Local ResourcesScsi Termination Watchdog Timer Programmable Tick TimersSoftware-Programmable Hardware Interrupts Local Bus to Dram Cycle Times Module IdentiﬁcationTiming Performance Local Bus Time-outScsi Transfers ROM Cycle TimesLAN DMA Transfers Remote Status and ControlAEIA-232-D Interconnections Table A-1. EIA-232-D Interconnections Pin Signal Number Mnemonic Signal Name and DescriptionLevels of Implementation Number Mnemonic Signal Name and DescriptionPin Sample Conﬁgurations Signal AdaptationsFigure A-1. Middle-of-the-Road EIA-232-D Conﬁguration Figure A-2. Minimum EIA-232-D Connection Proper Grounding EIA-232-D Interconnections Description of 177Bug Overview of M68000 FirmwareDebugger General Information 177Bug Implementation AutobootAutoboot in progress... To abort hit Break ROMboot Network Boot Restarting the System Abort ResetBreak MPU Clock Speed Calculation SYSFAIL* Assertion/NegationMemory Requirements Terminal Input/Output Control Blocks Versus Sectors Disk I/O SupportDebugger General Information IOC IOP IOT MAR MAW Device Probe FunctionIOP Physical I/O to Disk Disk I/O via 177Bug Commands IOI Input/Output InquiryIOC I/O Control BO Bootstrap Operating SystemBH Bootstrap and Halt IOT I/O TeachDskcfig Disk I/O Error Codes Default 177Bug Controller and Device ParametersNetwork I/O Support UDP/IP Protocol Modules Intel 82596 LAN Coprocessor Ethernet DriverRARP/ARP Protocol Modules Bootp Protocol ModuleTftp Protocol Module Multiprocessor Control Register Mpcr Method Network Boot Control ModuleNetwork I/O Error Codes Multiprocessor SupportStatus codes that may be set by the bus master are Gcsr Method Diagnostic Facilities Test Group Description Table B-1. Diagnostic Test GroupsEntering Debugger Command Lines Using the 177Bug DebuggerBoldface strings Syntactic VariablesData Type Base IdentiÞer Examples Expression as a ParameterExpression Result In Hex String Numeric Value LiteralAddress Formats Address as a ParameterTable B-2. Debugger Address Parameter Formats Offset Registers 177BugMD 1327CDI Port Numbers IOP Entering and Debugging Programs177Bug Vector Table and Workspace Exception Vectors Used by 177Bug Hardware FunctionsVector Offset Exception 177Bug Facility Table B-3. Exception Vectors Used by 177BugUsing 177Bug Target Vector Table Creating a New Vector Table Except SUBQ.L 177Bug Generalized Exception Handler 177BugMD A7&30 Integer Data Types Floating Point SupportFloating Point Data Types This format would appear in memory as Single Precision RealExtended Precision Real Double Precision RealPacked Decimal Real Scientiﬁc Notation Additions to Flash CommandsDiagflash erase Flash Test Conﬁguration Acceptable EntriesErase Test Flash Fill TestDiagflash fill Flash Patterns TestFigure B-1. Three Possible Mapping Options Default Flash Test ConﬁgurationSflash Command Sflashl Pflash ff800000 ff9fffff ffa00000 177Bug Debugger Command Set Cnfg I M Table B-4. Debugger CommandsCommand Command Line Mnemonic Title Syntax BI Range B W LIOI CL ENV DNopa n Niot H aR n a PA nVER E Or SET nCDebugger General Information First Second Controller Type Disk/Tape Controller Modules SupportedController Device Disk/Tape Controller Default ConﬁgurationsController Address Device Device TypeController MVME323 -- Four DevicesController LUN Address Device LUN Device Type MVME328 -- Fourteen DevicesFloppy Types and Formats IOT Parameter IOT Command Parameters for Supported Floppy TypesOther Conﬁgure Board Information Block CommandsConfigure and Environment Commands ENV D Set Environment to Bug/Operating System= EFFFFFFF? Master Starting Address #2 = 00000000? ENV Parameter and Options Default Meaning of Default Table D-1. ENV Command ParametersLUN Network Auto Boot Memory Search Starting Address $02 refer to the Memory Requirements Accessible by the VMEbus. Default is Slave Ending Address #2 Master Ending Address #3 Short I/O VMEbus A16 Control Network Controller Modules Supported ENetwork Controller DataClun Dlun Controller Interface TypeCondition Possible Problem Try This Table F-1. Basic Troubleshooting StepsCTRL-Q Envd CR Set mmddyyhhmm CRSt CR Env CRDe CR Index Index IN-7 IN-8 IN-9 IN-10 XON/XOFF