Controls and Indicators, Abort Switch S1 | Motorola MVME177 specs

Operating Instructions

3

Introduction

This chapter provides necessary information to use the MVME177 module in a system configuration. This includes:

❏Controls and indicators

❏Memory maps

❏Software initialization of the module

Controls and Indicators

On the front panel of the MVME177 module are the following:

❏ABORT and RESET switches

❏FAIL, STAT, RUN, SCON, LAN,+12V (LAN power), SCSI, and VME indicators

ABORT Switch S1

When enabled by software, the recessed front panel ABORT switch generates an interrupt at a user-programmable level. It is normally used to abort program execution and return to the 177Bug debugger firmware located in the MVME177 EPROMs.

The ABORT switch interrupter in the VMEchip2 is an edge-sensitive interrupter connected to the ABORT switch. This interrupter is filtered to remove switch bounce.

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Motorola MVME177 manual Controls and Indicators, Abort Switch S1

Contents

MVME177 Single Board Computer Installation and Use Manual Restricted Rights Legend Preface Page Adjusting This equipment. Use extreme caution when handling, testingPage Contents Page Page Flash Fill Test B-48Flash Patterns Test B-49 List of Figures List of Tables Model Number Speed Major Differences IntroductionModel Designations MVME177 Model Designations MVME177 Features FeaturesFeature Description Cooling Requirements Speciﬁcations MVME177 Speciﬁcations Characteristics SpeciÞcations FCC Compliance General Description MVME712AM Bbram MVME712M MVME712A MVME712AM MVME712B Equipment Required System V/68 Related Documentation Document Title Number Motorola Support Information Manual Terminology Unpacking Instructions Hardware Preparation and Installation Start-up Overview Overview of Start-up ProcedureWhat you will need to do Refer to Examine and/or change AppearsYou may also wish to obtain Initialize the clock Hardware Preparation MVME177 Switches, Headers, Connectors, Polyswitches LEDs Header Number Description ConÞguration Jumpers Conﬁguring MVME177 Headers 1MB Eprom MVME177 Header Notes Header Number Description ConÞguration Do not remove all jumpers from J2. This may Disable the Sram Setup Instructions Bit J1 Pins Description MVME177 Module Installation Instructions MVME177 Module Installation Instructions Hardware Preparation and Installation System Considerations Hardware Preparation and Installation MVME177 Module Installation Instructions Hardware Preparation and Installation Abort Switch S1 Controls and Indicators Reset Switch S2 Front Panel Indicators DS1 DS4 Local Bus Memory Map Memory MapsNormal Address Range Local Bus Memory Map Range Devices Accessed Port Size InhibitSoftware Address Local I/O Devices Memory Map Address Range Devices Accessed Port Size $FFF77000 $FFF77FFF Reserved Software Initialization Local Reset OperationMulti-MPU Programming Considerations Sysreset Operating Instructions MVME177 Functional Description Functional Description IntroductionData Bus Structure MPU Scsi Block Flash Memory and Eprom MC68060 MPUFlash Memory Jumper or Control Bit Control Condition Memory ConÞguration Eprom and Flash Control and Conﬁguration Eprom Sram Do not short circuit Onboard Dram Battery Backed Up RAM and Clock Interfaces VMEbus Interface RXD CTS DCD TXD RTS DTR Serial Port Interface TXD RTS DTR Parallel Port Interface Ethernet Interface Scsi Interface Local ResourcesScsi Termination Watchdog Timer Programmable Tick TimersSoftware-Programmable Hardware Interrupts Local Bus to Dram Cycle Times Module IdentiﬁcationTiming Performance Local Bus Time-out Scsi Transfers ROM Cycle Times LAN DMA Transfers Remote Status and Control AEIA-232-D Interconnections Table A-1. EIA-232-D Interconnections Pin Signal Number Mnemonic Signal Name and Description Levels of Implementation Number Mnemonic Signal Name and DescriptionPin Sample Conﬁgurations Signal Adaptations Figure A-1. Middle-of-the-Road EIA-232-D Conﬁguration Figure A-2. Minimum EIA-232-D Connection Proper Grounding EIA-232-D Interconnections Description of 177Bug Overview of M68000 Firmware Debugger General Information 177Bug Implementation Autoboot Autoboot in progress... To abort hit Break ROMboot Network Boot Restarting the System Abort Reset Break MPU Clock Speed Calculation SYSFAIL* Assertion/Negation Memory Requirements Terminal Input/Output Control Blocks Versus Sectors Disk I/O Support Debugger General Information IOC IOP IOT MAR MAW Device Probe Function IOP Physical I/O to Disk Disk I/O via 177Bug Commands IOI Input/Output Inquiry IOC I/O Control BO Bootstrap Operating SystemBH Bootstrap and Halt IOT I/O Teach Dskcfig Disk I/O Error Codes Default 177Bug Controller and Device ParametersNetwork I/O Support UDP/IP Protocol Modules Intel 82596 LAN Coprocessor Ethernet Driver RARP/ARP Protocol Modules Bootp Protocol ModuleTftp Protocol Module Multiprocessor Control Register Mpcr Method Network Boot Control ModuleNetwork I/O Error Codes Multiprocessor Support Status codes that may be set by the bus master are Gcsr Method Diagnostic Facilities Test Group Description Table B-1. Diagnostic Test Groups Entering Debugger Command Lines Using the 177Bug Debugger Boldface strings Syntactic Variables Data Type Base IdentiÞer Examples Expression as a Parameter Expression Result In Hex String Numeric Value Literal Address Formats Address as a ParameterTable B-2. Debugger Address Parameter Formats Offset Registers 177BugMD 1327CDI Port Numbers IOP Entering and Debugging Programs 177Bug Vector Table and Workspace Exception Vectors Used by 177Bug Hardware Functions Vector Offset Exception 177Bug Facility Table B-3. Exception Vectors Used by 177Bug Using 177Bug Target Vector Table Creating a New Vector Table Except SUBQ.L 177Bug Generalized Exception Handler 177BugMD A7&30 Integer Data Types Floating Point SupportFloating Point Data Types This format would appear in memory as Single Precision Real Extended Precision Real Double Precision RealPacked Decimal Real Scientiﬁc Notation Additions to Flash Commands Diagflash erase Flash Test Conﬁguration Acceptable EntriesErase Test Flash Fill Test Diagflash fill Flash Patterns Test Figure B-1. Three Possible Mapping Options Default Flash Test Conﬁguration Sflash Command Sflashl Pflash ff800000 ff9fffff ffa00000 177Bug Debugger Command Set Cnfg I M Table B-4. Debugger CommandsCommand Command Line Mnemonic Title Syntax BI Range B W L IOI CL ENV D Nopa n Niot H aR n a PA n VER E Or SET nC Debugger General Information First Second Controller Type Disk/Tape Controller Modules Supported Controller Device Disk/Tape Controller Default ConﬁgurationsController Address Device Device Type Controller MVME323 -- Four Devices Controller LUN Address Device LUN Device Type MVME328 -- Fourteen Devices Floppy Types and Formats IOT Parameter IOT Command Parameters for Supported Floppy Types Other Conﬁgure Board Information Block Commands Configure and Environment Commands ENV D Set Environment to Bug/Operating System = EFFFFFFF? Master Starting Address #2 = 00000000? ENV Parameter and Options Default Meaning of Default Table D-1. ENV Command Parameters LUN Network Auto Boot Memory Search Starting Address $02 refer to the Memory Requirements Accessible by the VMEbus. Default is Slave Ending Address #2 Master Ending Address #3 Short I/O VMEbus A16 Control Network Controller Modules Supported ENetwork Controller Data Clun Dlun Controller Interface Type Condition Possible Problem Try This Table F-1. Basic Troubleshooting Steps CTRL-Q Envd CR Set mmddyyhhmm CR St CR Env CRDe CR Index Index IN-7 IN-8 IN-9 IN-10 XON/XOFF