Motorola MVME177 manual Remote Status and Control, LAN DMA Transfers

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Functional Description

LAN DMA Transfers

The MVME177 includes a LAN interface with DMA controller. The LAN DMA controller uses a FIFO buffer to interface the serial LAN bus to the 32-bit local bus. The FIFO buffer allows the LAN DMA controller to efficiently transfer data to the local bus.

The 82596CA does not execute MC68060 compatible burst cycles, therefore the LAN DMA controller does not use burst transfers. DRAM write cycles require 3 clock cycles, and read cycles require:

❏5 clock cycles with parity off and

❏6 clock cycles with parity on

The transfer rate of the LAN DMA controller is 20MB/sec at 25 MHz (or 24MB/sec at 30 MHz) with parity off. Assuming a continuous transfer rate of 1MB/sec on the LAN bus, 5% (or 4%) of the local bus bandwidth is used by transfers from the LAN bus.

Remote Status and Control

The remote status and control connector, J3, is a 20-pin connector located behind the front panel of the MVME177. It provides system designers the flexibility to access critical indicator and reset functions. This allows a system designer to construct a RESET/ABORT/LED panel that can be located remotely from the MVME177.

In addition to the LED and the RESET and ABORT switches access, this connector also includes:

❏Two general purpose TTL-level I/O pins

❏One general purpose interrupt pin which can also function as a trigger input. This interrupt pin is level programmable

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