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MVME177 Functional Description
onboard DRAM require 5 bus clock cycles with the bus error reported in the current cycle. Write accesses to onboard DRAM require 2 bus clock cycles.
Burst read accesses require 8
ROM Cycle Times
The ROM cycle time is programmable from 4 to 11 bus clock cycles. The data transfers are 32 bits wide. Refer to the Single Board Computers Programmer's Reference Guide.
SCSI Transfers
The MVME177 includes a SCSI mass storage bus interface with DMA controller. The SCSI DMA controller uses a FIFO buffer to interface the
The first longword transfer of a burst, with snooping disabled, requires:
❏Four bus clocks with parity off, and
❏Five bus clocks with parity on
Each of the remaining three transfers requires one bus clock.
The transfer rate of the DMA controller is 44MB/sec at 25 MHz with parity off. Assuming a continuous transfer rate of 5MB/sec on the SCSI bus, 12% of the local bus bandwidth is used by transfers from the SCSI bus.
Note The actual SCSI bus transfer rate is fixed, no matter what the speed of the microprocessor.
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