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Motorola MVME177 manual Preface

Models: MVME177

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Preface

The MVME177 UserÕs Manual provides general information, hardware preparation and installation instructions, operating instructions, and functional description for the MVME177 Single Board Computer (referred to as MVME177 throughout this manual). The information contained in this manual applies to the following MVME177 models:

MVME177-001 MVME177-011

MVME177-002 MVME177-012

MVME177-003 MVME177-013

MVME177-004 MVME177-014

MVME177-005 MVME177-015

MVME177-006 MVME177-016

This manual is intended for anyone who wants to design OEM systems, supply additional capability to an existing compatible system, or work in a lab environment for experimental purposes.

A basic knowledge of computers and digital logic is assumed.

To use this manual, you should be familiar with the publications listed in the Related Documentation section in Chapter 1 of this manual.

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Motorola MVME177 manual Preface

Contents

MVME177 Single Board Computer Installation and Use ManualRestricted Rights Legend Preface Page Adjusting This equipment. Use extreme caution when handling, testingPage Contents Page Page Flash Fill Test B-48Flash Patterns Test B-49 List of Figures List of Tables Model Number Speed Major Differences IntroductionModel Designations MVME177 Model DesignationsFeatures MVME177 FeaturesFeature Description Cooling Requirements SpeciﬁcationsMVME177 Speciﬁcations Characteristics SpeciÞcationsFCC Compliance General DescriptionMVME712AM Bbram MVME712M MVME712A MVME712AM MVME712B Equipment RequiredSystem V/68 Related DocumentationDocument Title Number MotorolaSupport Information Manual Terminology Unpacking Instructions Hardware Preparation and InstallationOverview of Start-up Procedure Start-up OverviewWhat you will need to do Refer to Examine and/or change AppearsYou may also wish to obtain Initialize the clockHardware Preparation MVME177 Switches, Headers, Connectors, Polyswitches LEDs Header Number Description ConÞguration Jumpers Conﬁguring MVME177 Headers1MB Eprom MVME177 Header Notes Header Number Description ConÞgurationDo not remove all jumpers from J2. This may Disable the Sram Setup Instructions Bit J1 Pins Description MVME177 Module Installation Instructions MVME177 Module Installation Instructions Hardware Preparation and Installation System Considerations Hardware Preparation and Installation MVME177 Module Installation Instructions Hardware Preparation and Installation Abort Switch S1 Controls and IndicatorsReset Switch S2 Front Panel Indicators DS1 DS4 Memory Maps Local Bus Memory MapNormal Address Range Range Devices Accessed Port Size Inhibit Local Bus Memory MapSoftware Address Local I/O Devices Memory Map Address Range Devices Accessed Port Size$FFF77000 $FFF77FFF Reserved Local Reset Operation Software InitializationMulti-MPU Programming Considerations Sysreset Operating Instructions Functional Description Introduction MVME177 Functional DescriptionData Bus Structure MPU Scsi BlockMC68060 MPU Flash Memory and EpromFlash Memory Jumper or Control Bit Control Condition Memory ConÞguration Eprom and Flash Control and ConﬁgurationEprom Sram Do not short circuit Onboard Dram Battery Backed Up RAM and Clock Interfaces VMEbus InterfaceRXD CTS DCD TXD RTS DTR Serial Port InterfaceTXD RTS DTR Parallel Port Interface Ethernet Interface Local Resources Scsi InterfaceScsi Termination Programmable Tick Timers Watchdog TimerSoftware-Programmable Hardware Interrupts Local Bus to Dram Cycle Times Module IdentiﬁcationTiming Performance Local Bus Time-outScsi Transfers ROM Cycle TimesLAN DMA Transfers Remote Status and ControlAEIA-232-D Interconnections Table A-1. EIA-232-D Interconnections Pin Signal Number Mnemonic Signal Name and DescriptionNumber Mnemonic Signal Name and Description Levels of ImplementationPin Sample Conﬁgurations Signal AdaptationsFigure A-1. Middle-of-the-Road EIA-232-D Conﬁguration Figure A-2. Minimum EIA-232-D Connection Proper Grounding EIA-232-D Interconnections Description of 177Bug Overview of M68000 FirmwareDebugger General Information 177Bug Implementation AutobootAutoboot in progress... To abort hit Break ROMboot Network Boot Restarting the System Abort ResetBreak MPU Clock Speed Calculation SYSFAIL* Assertion/NegationMemory Requirements Terminal Input/Output Control Blocks Versus Sectors Disk I/O SupportDebugger General Information IOC IOP IOT MAR MAW Device Probe FunctionIOP Physical I/O to Disk Disk I/O via 177Bug Commands IOI Input/Output InquiryIOC I/O Control BO Bootstrap Operating SystemBH Bootstrap and Halt IOT I/O TeachDskcfig Default 177Bug Controller and Device Parameters Disk I/O Error CodesNetwork I/O Support UDP/IP Protocol Modules Intel 82596 LAN Coprocessor Ethernet DriverBootp Protocol Module RARP/ARP Protocol ModulesTftp Protocol Module Multiprocessor Control Register Mpcr Method Network Boot Control ModuleNetwork I/O Error Codes Multiprocessor SupportStatus codes that may be set by the bus master are Gcsr Method Diagnostic Facilities Test Group Description Table B-1. Diagnostic Test GroupsEntering Debugger Command Lines Using the 177Bug DebuggerBoldface strings Syntactic VariablesData Type Base IdentiÞer Examples Expression as a ParameterExpression Result In Hex String Numeric Value LiteralAddress as a Parameter Address FormatsTable B-2. Debugger Address Parameter Formats Offset Registers 177BugMD 1327CDI Port Numbers IOP Entering and Debugging Programs177Bug Vector Table and Workspace Exception Vectors Used by 177Bug Hardware FunctionsVector Offset Exception 177Bug Facility Table B-3. Exception Vectors Used by 177BugUsing 177Bug Target Vector Table Creating a New Vector Table Except SUBQ.L 177Bug Generalized Exception Handler 177BugMD A7&30 Floating Point Support Integer Data TypesFloating Point Data Types This format would appear in memory as Single Precision RealDouble Precision Real Extended Precision RealPacked Decimal Real Scientiﬁc Notation Additions to Flash CommandsDiagflash erase Flash Test Conﬁguration Acceptable EntriesErase Test Flash Fill TestDiagflash fill Flash Patterns TestFigure B-1. Three Possible Mapping Options Default Flash Test ConﬁgurationSflash Command Sflashl Pflash ff800000 ff9fffff ffa00000 177Bug Debugger Command Set Cnfg I M Table B-4. Debugger CommandsCommand Command Line Mnemonic Title Syntax BI Range B W LIOI CL ENV DNopa n Niot H aR n a PA nVER E Or SET nCDebugger General Information First Second Controller Type Disk/Tape Controller Modules SupportedController Device Disk/Tape Controller Default ConﬁgurationsController Address Device Device TypeController MVME323 -- Four DevicesController LUN Address Device LUN Device Type MVME328 -- Fourteen DevicesFloppy Types and Formats IOT Parameter IOT Command Parameters for Supported Floppy TypesOther Conﬁgure Board Information Block CommandsConfigure and Environment Commands ENV D Set Environment to Bug/Operating System= EFFFFFFF? Master Starting Address #2 = 00000000? ENV Parameter and Options Default Meaning of Default Table D-1. ENV Command ParametersLUN Network Auto Boot Memory Search Starting Address $02 refer to the Memory Requirements Accessible by the VMEbus. Default is Slave Ending Address #2 Master Ending Address #3 Short I/O VMEbus A16 Control Network Controller Modules Supported ENetwork Controller DataClun Dlun Controller Interface TypeCondition Possible Problem Try This Table F-1. Basic Troubleshooting StepsCTRL-Q Envd CR Set mmddyyhhmm CREnv CR St CRDe CR Index Index IN-7 IN-8 IN-9 IN-10 XON/XOFF