4

Functional Description

Two mezzanine boards may be stacked to provide 256MB of onboard RAM. The main board and a single mezzanine board together take one slot. The stacked configuration requires two VMEboard slots. The DRAM is four-way interleaved to efficiently support cache burst cycles.

The DRAM map decoder can be programmed to accommodate different base address(es) and sizes of mezzanine boards. The onboard DRAM is disabled by a local bus reset and must be programmed before the DRAM can be accessed. Refer to the MCECC in the Single Board Computers Programmer's Reference Guide for detailed programming information. Most DRAM devices require some number of access cycles before the DRAMs are fully operational. Normally this requirement is met by the onboard refresh circuitry and normal DRAM initialization. However, software should insure a minimum of 10 initialization cycles are performed to each bank of RAM.

Battery Backed Up RAM and Clock

The DS1643/MK48T08 RAM and clock chip is used on the MVME177. This chip provides the following items, all in one 28-pin package:

Time of day clock

Oscillator

Crystal

Power fail detection

Memory write protection

8KB of RAM

A battery

The clock provides:

Seconds

4-10

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Image 62
Motorola MVME177 manual Battery Backed Up RAM and Clock