MVME712AM | Motorola MVME177 specs

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General Information

❏One parallel port

❏A 16/A24/A32/D8/D16/D32/D64 VMEbus master/slave interface

❏128KB of static RAM (with optional battery backup), and VMEbus system controller.

The I/O on the MVME177 is connected to the VMEbus P2 connector. The main board is connected through a P2 transition board and cables to the transition boards. The MVME177 supports the following transition boards:

❏MVME712-12

❏MVME712-13

❏MVME712M

❏MVME712A

❏MVME712AM

❏MVME712B

(referred to in this manual as MVME712x, unless separately specified).

The MVME712x transition boards provide configuration headers and industry standard connectors for the I/O devices.

The VMEbus interface is provided by an ASIC called the

VMEchip2. The VMEchip2 includes:

❏Two tick timers

❏A watchdog timer

❏Programmable map decoders for the master and slave interfaces

❏VMEbus to/from local bus DMA controller

❏VMEbus to/from local bus non-DMA programmed access interface

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Motorola MVME177 manual MVME712AM

Contents

Single Board Computer Installation and Use Manual MVME177 Restricted Rights Legend Preface Page This equipment. Use extreme caution when handling, testing AdjustingPage Contents Page Page Flash Fill Test B-48Flash Patterns Test B-49 List of Figures List of Tables MVME177 Model Designations IntroductionModel Designations Model Number Speed Major Differences Features MVME177 FeaturesFeature Description Speciﬁcations Cooling Requirements Characteristics SpeciÞcations MVME177 Speciﬁcations General Description FCC Compliance MVME712AM Bbram Equipment Required MVME712M MVME712A MVME712AM MVME712B Related Documentation System V/68 Motorola Document Title Number Support Information Manual Terminology Hardware Preparation and Installation Unpacking Instructions Overview of Start-up Procedure Start-up OverviewWhat you will need to do Refer to Initialize the clock AppearsYou may also wish to obtain Examine and/or change Hardware Preparation MVME177 Switches, Headers, Connectors, Polyswitches LEDs Conﬁguring MVME177 Headers Header Number Description ConÞguration Jumpers 1MB Eprom Header Number Description ConÞguration MVME177 Header Notes Do not remove all jumpers from J2. This may Disable the Sram Setup Instructions Bit J1 Pins Description MVME177 Module Installation Instructions MVME177 Module Installation Instructions Hardware Preparation and Installation System Considerations Hardware Preparation and Installation MVME177 Module Installation Instructions Hardware Preparation and Installation Controls and Indicators Abort Switch S1 Reset Switch S2 Front Panel Indicators DS1 DS4 Memory Maps Local Bus Memory MapNormal Address Range Range Devices Accessed Port Size Inhibit Local Bus Memory MapSoftware Address Address Range Devices Accessed Port Size Local I/O Devices Memory Map $FFF77000 $FFF77FFF Reserved Local Reset Operation Software InitializationMulti-MPU Programming Considerations Sysreset Operating Instructions Functional Description Introduction MVME177 Functional DescriptionData Bus Structure MPU Block Scsi MC68060 MPU Flash Memory and EpromFlash Memory Eprom and Flash Control and Conﬁguration Jumper or Control Bit Control Condition Memory ConÞguration Eprom Sram Do not short circuit Onboard Dram Battery Backed Up RAM and Clock VMEbus Interface Interfaces Serial Port Interface RXD CTS DCD TXD RTS DTR TXD RTS DTR Parallel Port Interface Ethernet Interface Local Resources Scsi InterfaceScsi Termination Programmable Tick Timers Watchdog TimerSoftware-Programmable Hardware Interrupts Local Bus Time-out Module IdentiﬁcationTiming Performance Local Bus to Dram Cycle Times ROM Cycle Times Scsi Transfers Remote Status and Control LAN DMA Transfers AEIA-232-D Interconnections Pin Signal Number Mnemonic Signal Name and Description Table A-1. EIA-232-D Interconnections Number Mnemonic Signal Name and Description Levels of ImplementationPin Signal Adaptations Sample Conﬁgurations Figure A-1. Middle-of-the-Road EIA-232-D Conﬁguration Figure A-2. Minimum EIA-232-D Connection Proper Grounding EIA-232-D Interconnections Overview of M68000 Firmware Description of 177Bug Debugger General Information Autoboot 177Bug Implementation Autoboot in progress... To abort hit Break ROMboot Network Boot Restarting the System Reset Abort Break SYSFAIL* Assertion/Negation MPU Clock Speed Calculation Memory Requirements Terminal Input/Output Control Disk I/O Support Blocks Versus Sectors Debugger General Information Device Probe Function IOC IOP IOT MAR MAW Disk I/O via 177Bug Commands IOI Input/Output Inquiry IOP Physical I/O to Disk IOT I/O Teach BO Bootstrap Operating SystemBH Bootstrap and Halt IOC I/O Control Dskcfig Default 177Bug Controller and Device Parameters Disk I/O Error CodesNetwork I/O Support Intel 82596 LAN Coprocessor Ethernet Driver UDP/IP Protocol Modules Bootp Protocol Module RARP/ARP Protocol ModulesTftp Protocol Module Multiprocessor Support Network Boot Control ModuleNetwork I/O Error Codes Multiprocessor Control Register Mpcr Method Status codes that may be set by the bus master are Gcsr Method Diagnostic Facilities Table B-1. Diagnostic Test Groups Test Group Description Using the 177Bug Debugger Entering Debugger Command Lines Syntactic Variables Boldface strings Expression as a Parameter Data Type Base IdentiÞer Examples String Numeric Value Literal Expression Result In Hex Address as a Parameter Address FormatsTable B-2. Debugger Address Parameter Formats Offset Registers 177BugMD 1327CDI Port Numbers Entering and Debugging Programs IOP 177Bug Vector Table and Workspace Hardware Functions Exception Vectors Used by 177Bug Table B-3. Exception Vectors Used by 177Bug Vector Offset Exception 177Bug Facility Using 177Bug Target Vector Table Creating a New Vector Table Except SUBQ.L 177Bug Generalized Exception Handler 177BugMD A7&30 Floating Point Support Integer Data TypesFloating Point Data Types Single Precision Real This format would appear in memory as Double Precision Real Extended Precision RealPacked Decimal Real Additions to Flash Commands Scientiﬁc Notation Flash Fill Test Flash Test Conﬁguration Acceptable EntriesErase Test Diagflash erase Flash Patterns Test Diagflash fill Default Flash Test Conﬁguration Figure B-1. Three Possible Mapping Options Sflash Command Sflashl Pflash ff800000 ff9fffff ffa00000 177Bug Debugger Command Set BI Range B W L Table B-4. Debugger CommandsCommand Command Line Mnemonic Title Syntax Cnfg I M ENV D IOI CL PA n Niot H aR n a Nopa n Or SET nC VER E Debugger General Information Disk/Tape Controller Modules Supported First Second Controller Type Device Type Disk/Tape Controller Default ConﬁgurationsController Address Device Controller Device MVME323 -- Four Devices Controller MVME328 -- Fourteen Devices Controller LUN Address Device LUN Device Type IOT Command Parameters for Supported Floppy Types Floppy Types and Formats IOT Parameter Other Commands Conﬁgure Board Information Block Configure and Environment Commands Set Environment to Bug/Operating System ENV D = EFFFFFFF? Master Starting Address #2 = 00000000? Table D-1. ENV Command Parameters ENV Parameter and Options Default Meaning of Default LUN Network Auto Boot Memory Search Starting Address $02 refer to the Memory Requirements Accessible by the VMEbus. Default is Slave Ending Address #2 Master Ending Address #3 Short I/O VMEbus A16 Control ENetwork Controller Data Network Controller Modules Supported Controller Interface Type Clun Dlun Table F-1. Basic Troubleshooting Steps Condition Possible Problem Try This CTRL-Q Set mmddyyhhmm CR Envd CR Env CR St CRDe CR Index Index IN-7 IN-8 IN-9 IN-10 XON/XOFF