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Motorola MVME177 manual Table B-1. Diagnostic Test Groups, Test Group Description

Models: MVME177

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B

Debugger General Information

	Table B-1. Diagnostic Test Groups
Test Group	Description

RAM	Local RAM Tests

SRAM	Static RAM Tests

RTC	MK48T0x Real-Time Clock Tests

PCC2	Peripheral Channel Controller Tests

MCECC	Memory Board Tests

MEMC1	MC040 Memory Controller 1 ASIC Tests

MEMC2	MC040 Memory Controller 2 ASIC Tests

ST2401	CD2401 Serial Port Tests

CMMU	Cache and Memory Management Unit Tests

VME2	VME Interface ASIC VMEchip2 Tests

LANC	LAN Coprocessor (Intel 82596) Tests

NCR	NCR 53C710 SCSI I/O Processor Tests

FLASH	Flash Memory Tests

Notes 1. You may enter command names in either uppercase or lowercase.

2.Some diagnostics depend on restart defaults that are set up only in a particular restart mode. Refer to the documentation on a particular diagnostic for the correct mode.

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Motorola MVME177 manual Table B-1. Diagnostic Test Groups, Test Group Description

Contents

Single Board Computer Installation and Use Manual MVME177Restricted Rights Legend Preface Page This equipment. Use extreme caution when handling, testing AdjustingPage Contents Page Page Flash Fill Test B-48Flash Patterns Test B-49 List of Figures List of Tables MVME177 Model Designations IntroductionModel Designations Model Number Speed Major DifferencesMVME177 Features FeaturesFeature Description Speciﬁcations Cooling RequirementsCharacteristics SpeciÞcations MVME177 SpeciﬁcationsGeneral Description FCC ComplianceMVME712AM Bbram Equipment Required MVME712M MVME712A MVME712AM MVME712BRelated Documentation System V/68Motorola Document Title NumberSupport Information Manual Terminology Hardware Preparation and Installation Unpacking InstructionsStart-up Overview Overview of Start-up ProcedureWhat you will need to do Refer to Initialize the clock AppearsYou may also wish to obtain Examine and/or changeHardware Preparation MVME177 Switches, Headers, Connectors, Polyswitches LEDs Conﬁguring MVME177 Headers Header Number Description ConÞguration Jumpers1MB Eprom Header Number Description ConÞguration MVME177 Header NotesDo not remove all jumpers from J2. This may Disable the Sram Setup Instructions Bit J1 Pins Description MVME177 Module Installation Instructions MVME177 Module Installation Instructions Hardware Preparation and Installation System Considerations Hardware Preparation and Installation MVME177 Module Installation Instructions Hardware Preparation and Installation Controls and Indicators Abort Switch S1Reset Switch S2 Front Panel Indicators DS1 DS4 Local Bus Memory Map Memory MapsNormal Address Range Local Bus Memory Map Range Devices Accessed Port Size InhibitSoftware Address Address Range Devices Accessed Port Size Local I/O Devices Memory Map$FFF77000 $FFF77FFF Reserved Software Initialization Local Reset OperationMulti-MPU Programming Considerations Sysreset Operating Instructions MVME177 Functional Description Functional Description IntroductionData Bus Structure MPU Block ScsiFlash Memory and Eprom MC68060 MPUFlash Memory Eprom and Flash Control and Conﬁguration Jumper or Control Bit Control Condition Memory ConÞgurationEprom Sram Do not short circuit Onboard Dram Battery Backed Up RAM and Clock VMEbus Interface InterfacesSerial Port Interface RXD CTS DCD TXD RTS DTRTXD RTS DTR Parallel Port Interface Ethernet Interface Scsi Interface Local ResourcesScsi Termination Watchdog Timer Programmable Tick TimersSoftware-Programmable Hardware Interrupts Local Bus Time-out Module IdentiﬁcationTiming Performance Local Bus to Dram Cycle TimesROM Cycle Times Scsi TransfersRemote Status and Control LAN DMA TransfersAEIA-232-D Interconnections Pin Signal Number Mnemonic Signal Name and Description Table A-1. EIA-232-D InterconnectionsLevels of Implementation Number Mnemonic Signal Name and DescriptionPin Signal Adaptations Sample ConﬁgurationsFigure A-1. Middle-of-the-Road EIA-232-D Conﬁguration Figure A-2. Minimum EIA-232-D Connection Proper Grounding EIA-232-D Interconnections Overview of M68000 Firmware Description of 177BugDebugger General Information Autoboot 177Bug ImplementationAutoboot in progress... To abort hit Break ROMboot Network Boot Restarting the System Reset AbortBreak SYSFAIL* Assertion/Negation MPU Clock Speed CalculationMemory Requirements Terminal Input/Output Control Disk I/O Support Blocks Versus SectorsDebugger General Information Device Probe Function IOC IOP IOT MAR MAWDisk I/O via 177Bug Commands IOI Input/Output Inquiry IOP Physical I/O to DiskIOT I/O Teach BO Bootstrap Operating SystemBH Bootstrap and Halt IOC I/O ControlDskcfig Disk I/O Error Codes Default 177Bug Controller and Device ParametersNetwork I/O Support Intel 82596 LAN Coprocessor Ethernet Driver UDP/IP Protocol ModulesRARP/ARP Protocol Modules Bootp Protocol ModuleTftp Protocol Module Multiprocessor Support Network Boot Control ModuleNetwork I/O Error Codes Multiprocessor Control Register Mpcr MethodStatus codes that may be set by the bus master are Gcsr Method Diagnostic Facilities Table B-1. Diagnostic Test Groups Test Group DescriptionUsing the 177Bug Debugger Entering Debugger Command LinesSyntactic Variables Boldface stringsExpression as a Parameter Data Type Base IdentiÞer ExamplesString Numeric Value Literal Expression Result In HexAddress Formats Address as a ParameterTable B-2. Debugger Address Parameter Formats Offset Registers 177BugMD 1327CDI Port Numbers Entering and Debugging Programs IOP177Bug Vector Table and Workspace Hardware Functions Exception Vectors Used by 177BugTable B-3. Exception Vectors Used by 177Bug Vector Offset Exception 177Bug FacilityUsing 177Bug Target Vector Table Creating a New Vector Table Except SUBQ.L 177Bug Generalized Exception Handler 177BugMD A7&30 Integer Data Types Floating Point SupportFloating Point Data Types Single Precision Real This format would appear in memory asExtended Precision Real Double Precision RealPacked Decimal Real Additions to Flash Commands Scientiﬁc NotationFlash Fill Test Flash Test Conﬁguration Acceptable EntriesErase Test Diagflash eraseFlash Patterns Test Diagflash fillDefault Flash Test Conﬁguration Figure B-1. Three Possible Mapping OptionsSflash Command Sflashl Pflash ff800000 ff9fffff ffa00000 177Bug Debugger Command Set BI Range B W L Table B-4. Debugger CommandsCommand Command Line Mnemonic Title Syntax Cnfg I MENV D IOI CLPA n Niot H aR n a Nopa nOr SET nC VER EDebugger General Information Disk/Tape Controller Modules Supported First Second Controller TypeDevice Type Disk/Tape Controller Default ConﬁgurationsController Address Device Controller DeviceMVME323 -- Four Devices ControllerMVME328 -- Fourteen Devices Controller LUN Address Device LUN Device TypeIOT Command Parameters for Supported Floppy Types Floppy Types and Formats IOT ParameterOther Commands Conﬁgure Board Information BlockConfigure and Environment Commands Set Environment to Bug/Operating System ENV D= EFFFFFFF? Master Starting Address #2 = 00000000? Table D-1. ENV Command Parameters ENV Parameter and Options Default Meaning of DefaultLUN Network Auto Boot Memory Search Starting Address $02 refer to the Memory Requirements Accessible by the VMEbus. Default is Slave Ending Address #2 Master Ending Address #3 Short I/O VMEbus A16 Control ENetwork Controller Data Network Controller Modules SupportedController Interface Type Clun DlunTable F-1. Basic Troubleshooting Steps Condition Possible Problem Try ThisCTRL-Q Set mmddyyhhmm CR Envd CRSt CR Env CRDe CR Index Index IN-7 IN-8 IN-9 IN-10 XON/XOFF