Nortel Networks MSC8101 ADS Dummy Bidir, Variable, Hosten, Srff, Hrdshift, Datahold, EE0HOLD

Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.

D[0..7]	: BIDIR;	--	Bidirectional 8-bit wide Data Bus
DUMMY	: BIDIR;	--	Blank - Schematic’s bug workaround
)
VARIABLE
Bcsr0[0..SIZE0],
Bcsr1[0..SIZE1],
Bcsr4[2..SIZE4],	-- BCSR4		is utilized for MODCK reconfig - Service Register 1
Bcsr5[0..SIZE5],	-- BCSR5		is utilized to program synthesizer - Service Register 2
Bcsr6[0..SIZE6],	-- BCSR6		is utilized to program synthesizer - Service Register 3
WE0Spare,	--	*** Option ***
HOST_EN,

SyncHardReset,

DSyncHardReset,-- Double D-ff to double synchronize the HRESET input.

FlashOE,	-- optional Flash OE (BPOEb)
SyncTEA	-- optional cell for TEA~ line
	: DFF;
Data_Buff[0..SIZE0]
	: TRI;
DivEn,	-- Starter for divider to produce PONRESET pulse from clock
-- WDEn,	-- Starter for divider to produce WD
StartStopWD	-- Control WD
	: SRFF;
HRESET_FEdge	: lpm_counter WITH (LPM_WIDTH = 2, LPM_DIRECTION = “UP”);
SoftRstMachin,
AbortRstMachin,
HardRstMachin	: Reset_Ensure; --State Machines for Push Buttons
HRD_SHIFT	: lpm_shiftreg WITH (LPM_WIDTH = SHIFT_LENGTH);
DATA_HOLD	: lpm_counter WITH (LPM_WIDTH = 2, LPM_DIRECTION = “UP”);

%The Reset Ensure Code disables the debouncing of all 3 reset push buttons in case of 3 msec bouncing time (Equal count is 2^19)%

ResetEnsure	: lpm_counter WITH (LPM_WIDTH = 19, LPM_DIRECTION = “UP”);
PRST_Ensure	: lpm_counter WITH (LPM_WIDTH	= 5, LPM_DIRECTION = “UP”);
% Provide Altera safe Power-on-Reset to initiate BCSR4		register %
EE0_HOLD	: lpm_counter WITH (LPM_WIDTH = 12, LPM_DIRECTION = “UP”);

%Hold EE0 in high up to X clocks after HRESET becomes disasserted to enter the chip into the debug mode%

EE45_HOLD	: lpm_counter WITH		(LPM_WIDTH = 10, LPM_DIRECTION = “UP”);
% Hold EE4,EE5 setting up to X clocks after SRESET becomes disasserted for correct boot %
POR_IMPULSE1,	--	First 4 bit Stage
POR_IMPULSE2,	-- Second 4 bit Stage
WD_TIMER1,	--	WD first	4	bit stage
WD_TIMER2,	-- WD	second 4	bit stage
WD_TIMER3,	--	WD third	4	bit stage
WD_TIMER4,	--	WD forth	4	bit stage
WD_TIMER5,	--	WD fifth	4	bit stage
WD_TIMER6,	--	WD sixth	4	bit stage

WD_TIMER7,	-- WD seventh 4 bit stage
WD_TIMER8	-- WD eighth 4 bit stage
	: freqdiv; -- Dividers to provide PONRESET pulse from Clock Osc
SM73288X,	-- Flash Devices available
SM73248X,
SM73228X,
FLASH_BANK1,
FLASH_BANK2,
FLASH_BANK3,
FLASH_BANK4,
FIRST_CFG_BYTE_READ,

MOTOROLA MSC8101ADS RevB User’s ManualC-105

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