Nortel Networks MSC8101 ADS user manual Manual Soft Reset, IRQ2

Freescale Semiconductor, Inc.

			Freescale Semiconductor, Inc.
				Functional Description
		TABLE 5-2. Hard Reset Configuration Word
	Data		Prog							Offset In	Value
Field	Bus		Value		Implication					Flash
											[Hex]
	Bits		[Bin]							[Hex]
IRPC	8:9		’00’	Interrupt pin configuration. NC/BADDR(29)/						8	00
				IRQ2,NC/BADDR(30)/IRQ3,NC/BADDR(31)/
				IRQ5 are selected as NC (not connect)
DPPC	10:11		‘00’	Data Parity Pin configuration as
									IRQ[1:7].
NMIOUT	12		’0’	NMI interrupt is serviced by the core.
ISB	13:15		’000’	IMMR initial value 0x0, i.e., the internal space
				resides initially at address 0xF0000000
BMS	16		’0’	Non-functional cleared bit.						10	02
BBD	17		’0’	Bus busy pins set:
						AB	B/IRQ2	pin is ABB
				DBB/IRQ3 pin is DBB
Reserved	18:21		‘0000’	Must be cleared
TCPC	22:23		’10’	Transfer code pins are configured following
				way after	PONRESET:
				MODCK1/BNKSEL(0)/TC(0) as BKSEL0
				MODCK2/BNKSEL(1)/TC(1) as BKSEL1
				MODCK3/BNKSEL(2)/TC(2) as BKSEL2
BC1PC	24:25		’00’	Buffer control 1-pin configuration BCTL1/						18	1E
				DBG_DIS~ functions as BCTL1
Reserved	26		’0’	Reserved. Should be cleared.
DLLDISa	27		’1’	No DLL bypass when value is zero. Controlled
				with jumper JP1
MODCK_HI	28:30		‘111’	High-order bits of the MODCK array i.e.
				MODCK[4-6]. Set Clock Mode 57. See [4].
Reserved	31		’0’	Reserved. Should be cleared.

a. Applies only ONCE after power-up reset.

When HCW is applied from Flash (SW9/7 is ON) DLLDIS and MODCK_HI bits have value shown in ta- ble. In case of HCW source will be from BCSR (SW9/7 is OFF) those bits set up manually - DLLDIS is controlled by JP1 and MODCK_HI - by DIP-switch SW9/4-6.

5•1•4 Manual Soft Reset

To allow run-time Soft-reset, when the Command Converter is disconnected from the JTAG/ONCE connector and to support resident debuggers, a Soft Reset push-button is provided. When the Soft Reset push-button is depressed, the SRESET line is asserted to the MSC8101, generating a Soft Reset sequence.

Since the SRESET line may be driven internally by the MSC8101, it must be driven by an open- drain gate, to avoid contention over that line. If off-board H/W connected to the MSC8101ADS is to drive SRESET line, then, it should do so with an open-drain gate, this, to avoid contention over this line.

MOTOROLA MSC8101ADS RevB User’s Manual 41

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