Host I/F Setting SW1 | Nortel Networks MSC8101 ADS instruction

Inc.

Freescale Semiconductor, Inc.

Operating Instructions

4 - Operating Instructions

4•1 INTRODUCTION

This chapter provides necessary information to use the MSC8101-ADS in host-controlled and stand-alone configurations. This includes controls and indicators, memory map details, and software initialization of the board.

4•2 SWITCHES

The MSC8101ADS has the following switches:

4•2•1 Host I/F Setting - SW1

This switch is using for manually set a Host Bus parameters. When Host Configuration is enable the DIP switch SW1/1-3 will be connected to Data Bus through tri-state buffers and sampled by the Processor. The SW1 factory set is all ON.

FIGURE 4-1 Switch SW1 HOST - Description

Semiconductor,

RESERVED 8/16BIT

DualSingleStrobe

StrobePolarity

SW1

ON

4

3

2

1

Freescale

Set to ‘0’ <=

=> Set to ’1’

4•2•2 Emulator Enable (EE) - SW2

This switch controls lines EE0-EE7,EED, connected to appropriate pins of the Processor. When Reset Configuration executed, EEs lines, involved in one, are driven by FPGA. In fact, they are EE0, EE1, EE4 and EE5 which sampled at the rising edge of PORESET~. After configuration is done level of all EE-signals is set by the switch SW2/1-7. Their status may be read out via

BCSR3/0-6.SW2 is factory set to all ON.

26

MSC8101ADS RevB User’s Manual

MOTOROLA

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Image 26

Nortel Networks MSC8101 ADS user manual Host I/F Setting SW1, Emulator Enable EE SW2

Contents

MSC8101 ADS MSC8101ADS RevB User’s Manual Contents ATM on LD14 BOM Freescale Semiconductor, Inc List of Figures Viii List of Tables Freescale Semiconductor, Inc Related Documentation IntroductionAbbreviations’ List Characteristics Specifications SpecificationMSC8101ADS Specifications ADS Features Freescale Semiconductor, Inc Semiconductor, Inc Hardware Preparation MSC8101ADS Top Side Part Location diagram Setting HReset Configuration Source Setting The Core Supply Voltage LevelSetting MODCK13 For Initial PLLs’ Multiplication Factor SW9 OnCE Connection Scheme Host I/F Operation Stand Alone Operation Host System Debug Scheme B 34 +5V Power Supply Connection JTAG/OnCE Connector P6 Host I/F Connector P4 P6 JTAG/OnCE Port Connector P4 Host I/F Connector Terminal to MSC8101ADS RS-232 Connection Flash Memory Simm Installation 38 10/100-Base-T Ethernet Port Connection Flash Memory Simm Insertion Host I/F Setting SW1 Emulator Enable EE SW2 Data Bus Width Setting SW5 & SW6 Abort Switch SW3Soft Reset Sreset Switch SW4 Configuration Switch SW9 Hard Reset Hreset Switch SW7Power-On Reset Switch Preset SW8 Modck Available Clock Mode SettingBoot Mode Select SW10 CPM Jumpers Software Options Switch SW11431 JP1 DLL Disable 432 JP2 Clock Buffer Set 437 JP9 5V power supply for Codec 433 JP3 50 Ohm Enable436 JP6,JP7 MIC Enable 434 JP4 VPP Source Selector LEDs ATM RX Indicator LD6 Ethernet Link Indicator LD4Fast Ethernet Clsn Indicator LD5 ATM TX Indicator LD7 MSC8101’s Registers’ Programming Memory Controller Registers Programming SIU Registers’ ProgrammingSystem Initialization Memory Controller Initialization for 10050a MHz Memory Controller Initialization for 10050a MHz Mbmr Power On Reset Configuration Reset & Reset ConfigurationPower- On Reset Manual Hard Reset Summary Reset Configuration Schemes Hard Reset Configuration Word Manual Soft Reset IRQ2 Local Interrupter Clock Generator Bus Buffering Chip Select Generator Synchronous Dram Bank MSC8101ADS Chip Select Assignments Bus Timing Machine Sdram MHz Sdram Mode Register ProgrammingSdram Programming Sdram Refresh Cycle Type \ Flash Delay nsecFlash Memory Simm Flash Simm Connection Scheme Flash Programming Voltage Communication Ports Ports Function Enable MSC8101 I/O Ports/Name 581 ATM Port 582 100/10 Base T Port 5831 CS4221 Programming CS4221 ProgrammingAudio Codec 585 RS232 Ports CS4221 Programming584 T1/E1 Ports Host I/F Board Control & Status Register Bcsr Host I/F Interconnect signalsDMA off-board tool BIT Mnemonic BCSR0 DescriptionBCSR0 Board Control / Status Register PON ATT DEF Hostcsp BCSR1 Board Control / Status Register BCSR0 Description10. BCSR1 Description Fethien 10. BCSR1 DescriptionPON ATT DEF Atmrst Fethrst BCSR2 Board Control / Status Register 11. Peripheral’s Availability Decoding12. BCSR2 Description 14. Flash Presence Detect 41 Encoding 12. BCSR2 Description13. Flash Presence Detect 75 Encoding BCSR3 Board Status Register 15. BCSR3 Description 18. ADS Revision Encoding 16. EXTOOLI03 Assignment17. External Tool Revision Encoding Engineering PPC Bus Memory Map MSC8101ADS Memory Map FF000000 Ffffffff MSC8101ADS Memory MapFE000000 Ffffffff FF800000 Ffffffff Power rails ADS Power Scheme 712 3V Bus Off-Board Application Maximum Current Consumption711 5V Bus 713 5V Bus Appendix a MSC8101 Bill of Material A1 BOM Table A-1. MSC8101ADS Bill Of Material Freescale Inc Inc Dale Freescale Semiconductor Freescale Semiconductor, Inc Appendix B Support Information Interconnect Signals B11 Table B1-2. P1 System Expansion Interconnect Signals TSTAT1 GNDTSTAT0 TSTAT2 TSTAT3 TSTAT4 TSTAT5 Clkx Damage to the PM5350 ATM UNI EXPD2 EXPD0EXPD1 EXPD3 EXPCTL0 SCC1RXD PD30 Table B1-3. P2 CPM Expansion Interconnect SignalsB12 MSC8101ADS’s P2 CPM Expansion Connector Hwrds SPICLKPD18SPIMOSIPD17 PD7 Atmrfclk Atmtsoc PA29Atmrsoc PA27 Atmrca PA26 ATMRXD5 PA15 ATMRXD7 PA17ATMRXD6 PA16 ATMRXD4 PA14 Fethcol PB27 Fethtxen PB29Fethrxer PB28 Fethcrs PB26 HD2 HD0HD1 HD3 Atmfclk PC26 Fethmdc PC13 PC6 Fethmdio PC12PC7 SMCTX1PC5 B13 Table B1-4. P3 ISP Connector Interconnect SignalsB14 P4 Host Interface Connector Hack HD1 HD2 HD3 HD4 HD5 HD6 HD7 HD8 HD9HA1 HA2 HA3 HCS1 Hreq B16 Table B1-6. P6 JTAG/ONCE Connector Interconnect SignalsB15 P5, P7, P8, P9, P10, P13, P14 Logic Analyzer Connectors HDS B18 P15,P16 SMB Connectors Table B1-7. P12 Ethernet Port Interconnect SignalsB17 P12 Ethernet Port Connector B19 P17,P18 Double RJ45 T1/E1 Line Connectors B110 P19,P21,P24 Stereo Phone Jack Connectors B111 P20,P22,P23,P25 RCA Jack Connectors B112 P26 5V Power Supply Connectors Table B1-10. P27A Interconnect SignalsTable B1-11. P27B Interconnect Signals B113 P27A,B RS232 Ports’ Connectors Freescale Semiconductor, Inc Appendix C Program Information Freescale Semiconductor, Inc Logic Equations C11 First Include File C12 Second Include file C13 Main File Constant SIZE1 Constant SHIFTLENGTH= Length of HRD/HRW Delay Shifter SIZE0Constant EE45HOLDVALUE Constant SRESET~ Constant TCPCDEFAULT0 Constant TCPCDEFAULT1HDIMDEN~ Host SW Enable RSTCNF~ Output HRESET~ Bidir HDIEN~ SBOOTENOUT~SPARE1 Output HRRQEN~ WDTIMER3 WDTIMER1WDTIMER2 WDTIMER4 BCSR1 SBOOTEN~ EepromenableResets Cleartowdctrl Scndcfgbyteread Thirdcfgbyteread Fourthcfgbyteread BCSR1PONDEF0..SIZE1 BCSR3IRQ0 BCSR3PONDEF0..SIZE3 BCSR0 BCSR0PONCONST0..5 Begin DefaultsEND Defaults END if END Generate EEDPONDEFAULT,RSV37PONDEFAULTElse PSDVAL~ = Opndrnvcc EE PinsRegularpoweronreset = RPORI~ == Regularponresetactive END if Else Hdiwr = If Hdds thenIf !HDSP then Hdiwr = END if Else Elsif MPCWRITEBCSR5 then Elsif MPCWRITEBCSR1 thenElsif MPCWRITEBCSR4 then Elsif MPCWRITEBCSR6 then Elsif MPCREADBCSR3 then SIGNALLAMP1~ Elsif MPCREADBCSR1 thenIf MPCREADBCSR0 then Elsif Firstcfgbyteread then HRESET~ =SRESET~ = Elsif Scndcfgbyteread then Else SIGLAMP1OUT~ Then SIGLAMP0OUT~ = GND ElseThen SIGLAMP1OUT~ END if If !T1234EN~ & FETHIEN~ then 116 MODCK1-3 Driven END if Drive Poreset Impulse Reconfig Using BCSR4Watchdog for Auto Reconfiguration 118