Nortel Networks MSC8101 ADS user manual Memory Controller Initialization for 10050a MHz

Freescale Semiconductor, Inc.

Operating Instructions

Warning

The initialization in TABLE 4-4. "Memory Control- ler Initialization for 100(50) MHz" below are based on design and are not verified yet, due to silicon availability problems.

TABLE 4-4. Memory Controller Initialization for 100(50)a MHz

		Reg.	Device Type		Bus	Init Value	Description
						[hex]
	BR0		SM73228XG1JHBG0	by		FF801801	Base at FF800000, 32 bit port size, no parity,
			Smart Modular Tech.				GPCM
			SM73248XG2JHBG0	by		FF001801	Base at FF00000, 32 bit port size, no parity,
Inc.			Smart Modular Tech.				GPCM
			SM73288XG4JHBG0	by	Buffered	FE001801	Base at FE00000, 32	bit port size, no parity,
			Smart Modular Tech.				GPCM
					PPC
Semiconductor,	OR0		SM73228XG1JHBG0	by		FF800866	8MByte block size, CS early negate, 12(6) w.s.,
			Smart Modular Tech.			(FF800836)	Timing relax
			SM73248XG2JHBG0	by		FF000866	16MByte block size, CS early negate, 12(6) w.s.,
			Smart Modular Tech.			(FF000836)	Timing relax
			SM73288XG4JHBG0	by		FE000866	32MByte block size, CS early negate, 12(6) w.s.,
			Smart Modular Tech.			(FE000836)	Timing relax
	BR1				Buffered	14501801	Base at 14500000, 32 bit port size, no parity,
			BCSR0-3		PPC		GPCM
	OR1					FFFF8010	32 KByte block size, all types access, 1 w.s.
						(FFFF8020)	(32 KByte block size, all types access, 2 w.s.)
Freescale	BR2		SDRAM 64bit Supported		Non-buffered	20000041	Base at 20000000, 64 bit port size, no parity,
					PPC		SDRAM machine 1
	OR2b		MT48LC2M32B2T6-8	by		FF803280	8MByte block size, 4 banks per device, row starts
	OR2		MT48LC2M32B2T6-8x2			FF003080	16MByte block size, 4 banks per device, row starts
			by Micron				at A8, 11 row lines, internal bank interleaving
							allowed
	BR2b		SDRAM 32bit Supported		Non-buffered	20001841	Base at 20000000, 32 bit port size, no parity,
					PPC with		SDRAM machine 1
					Host support
			Micron				at A9, 11 row lines, internal bank interleaving
							allowed
	BR3c		SDRAM 32bit Supported		Non-buffered	20801841	Base at 20800000, 32 bit port size, no parity,
					PPC with		SDRAM machine 1
					Host support
	OR3c		MT48LC2M32B2T6-8	by		FF803280	8MByte block size, 4 banks per device, row starts
			Micron				at A9, 11 row lines, internal bank interleaving
							allowed
	BR4		QFALC - 4ch. T1/E1		Buffered	146088A1	Base at 14608000, 8 bit port size, no parity, UPMB
					PPC		on PPC bus
	OR4					FFFF8106	32K Byte block size, burst inhibit, eight idle cycle
							are inserted before next access
	36			MSC8101ADS RevB User’s Manual				MOTOROLA

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