PSDVAL~ = Opndrnvcc, EE Pins, END if | Nortel Networks MSC8101 ADS

Freescale Semiconductor, Inc.

	Freescale Semiconductor, Inc.
WE0Spare.clk = GLOBAL(clock);
SyncTEA.d = VCC;		-- for optional use
TEA~ = OPNDRN(SyncTEA.q);
FlashOE.d= VCC;
BPOE~= OPNDRN(FlashOE);
PSDVAL~ = OPNDRN(VCC);
WE0Spare.d= VCC;
WE0 = OPNDRN(WE0Spare);
%*************************************
EE PINS
*************************************%
EE0_HOLD.aclr = !HRESET~;
EE0_HOLD_END = (EE0_HOLD.q[] == EE0_HOLD_VALUE); -- terminal count
IF(EE0_HOLD_END & HRESET~) THEN EE0_HOLD.cnt_en = GND; -- Disable count after term value
ELSE		EE0_HOLD.cnt_en = VCC;
END IF;
EE45_HOLD.aclr = !SRESET~;		-- Holding Boot Mode Setting (EE4,EE5) after negation SRESET
EE45_HOLD_END = (EE45_HOLD.q[] == EE45_HOLD_VALUE); -- terminal count
IF(EE45_HOLD_END & SRESET~) THEN EE45_HOLD.cnt_en = GND; -- Disable count after term value
ELSE		EE45_HOLD.cnt_en = VCC;
END IF;
EE0 = TRI((DBGEN~==GND),(!HRESET~ or !EE0_HOLD_END)); -- EE0 delayed to N-clocks
--TRI((DBGEN~==GND),(RESETi or !SRESET~)); !!!!!!
EE1 = TRI(!HOSTCFG~,RESETi); -- Assign HPE (Via EE1 net)
EE2= TRI(GND, GND);
EE3= TRI(GND, GND);
EE4= TRI((BTM0==VCC),(RESETi or !SRESET~ or !EE45_HOLD_END));
EE5= TRI((BTM1==VCC),(RESETi or !SRESET~ or !EE45_HOLD_END));
EED= TRI(GND, GND);
RSTCNF~ = TRI((!HOSTCFG~), RESETi); -- RSTCNF~ IS ENABLED(depends on HOSTCFG)
		-- on R_PORI~ rise.
		-- ver 2.0
REGULAR_POWER_ON_RESET = (R_PORI~ == REGULAR_PON_RESET_ACTIVE);
SyncHardReset.d = HRESET~; -- Check for Hard Reset
DSyncHardReset.d = SyncHardReset.q;
HARD_RESET_ACTIVE~ = DSyncHardReset.q;
%********************************
*******	HOST Assignments *******
********************************%
HOST_EN.d= !HOSTCFG~ and HOSTPD;
HDILED~ = OPNDRN(!HOST_EN);
HDI_EN~	= !HOST_EN;
HRRQ_EN~= !HOSTRQAC OR HDI_EN~ OR HOSTTRI;
HACK_EN~= HOSTRQAC OR HDI_EN~ OR HOSTTRI;
HDIMDEN~= !HOST_EN OR REGULAR_POWER_ON_RESET;
HRD_SHIFT.enable= VCC;
IF(!DSyncHardReset.q) THEN HRD_SHIFT.aclr = VCC;--CLEAR SH-REG in case of Hard Reset

C-110	MSC8101ADS RevB User’s Manual		MOTOROLA
		For More Information On This Product,
		Go to: www.freescale.com

Image 111

Nortel Networks MSC8101 ADS PSDVAL~ = Opndrnvcc, EE Pins, END if, EE2= TRIGND, GND EE3= TRIGND, GND, Eed= Trignd, Gnd

Contents

MSC8101 ADS MSC8101ADS RevB User’s Manual Contents ATM on LD14 BOM Freescale Semiconductor, Inc List of Figures Viii List of Tables Freescale Semiconductor, Inc Introduction Abbreviations’ ListRelated Documentation Specification MSC8101ADS SpecificationsCharacteristics Specifications ADS Features Freescale Semiconductor, Inc Semiconductor, Inc Hardware Preparation MSC8101ADS Top Side Part Location diagram Setting The Core Supply Voltage Level Setting MODCK13 For Initial PLLs’ Multiplication Factor SW9Setting HReset Configuration Source Host I/F Operation OnCE Connection Scheme Host System Debug Scheme B Stand Alone Operation JTAG/OnCE Connector P6 34 +5V Power Supply Connection P6 JTAG/OnCE Port Connector Host I/F Connector P4 Terminal to MSC8101ADS RS-232 Connection P4 Host I/F Connector 38 10/100-Base-T Ethernet Port Connection Flash Memory Simm Installation Flash Memory Simm Insertion Emulator Enable EE SW2 Host I/F Setting SW1 Abort Switch SW3 Soft Reset Sreset Switch SW4Data Bus Width Setting SW5 & SW6 Hard Reset Hreset Switch SW7 Power-On Reset Switch Preset SW8Configuration Switch SW9 CPM Available Clock Mode SettingBoot Mode Select SW10 Modck 432 JP2 Clock Buffer Set Software Options Switch SW11431 JP1 DLL Disable Jumpers 434 JP4 VPP Source Selector 433 JP3 50 Ohm Enable436 JP6,JP7 MIC Enable 437 JP9 5V power supply for Codec LEDs ATM TX Indicator LD7 Ethernet Link Indicator LD4Fast Ethernet Clsn Indicator LD5 ATM RX Indicator LD6 MSC8101’s Registers’ Programming SIU Registers’ Programming System InitializationMemory Controller Registers Programming Memory Controller Initialization for 10050a MHz Memory Controller Initialization for 10050a MHz Mbmr Manual Hard Reset Reset & Reset ConfigurationPower- On Reset Power On Reset Configuration Hard Reset Configuration Word Summary Reset Configuration Schemes IRQ2 Manual Soft Reset Clock Generator Local Interrupter Chip Select Generator Bus Buffering MSC8101ADS Chip Select Assignments Bus Timing Machine Synchronous Dram Bank MHz Sdram Mode Register Programming Sdram ProgrammingSdram Cycle Type \ Flash Delay nsec Flash Memory SimmSdram Refresh Flash Programming Voltage Flash Simm Connection Scheme Communication Ports MSC8101 I/O Ports/Name Ports Function Enable 582 100/10 Base T Port 581 ATM Port CS4221 Programming Audio Codec5831 CS4221 Programming CS4221 Programming 584 T1/E1 Ports585 RS232 Ports Host I/F Host I/F Interconnect signals DMA off-board toolBoard Control & Status Register Bcsr PON ATT DEF Hostcsp BCSR0 DescriptionBCSR0 Board Control / Status Register BIT Mnemonic BCSR0 Description 10. BCSR1 DescriptionBCSR1 Board Control / Status Register Fethrst 10. BCSR1 DescriptionPON ATT DEF Atmrst Fethien 11. Peripheral’s Availability Decoding 12. BCSR2 DescriptionBCSR2 Board Control / Status Register BCSR3 Board Status Register 12. BCSR2 Description13. Flash Presence Detect 75 Encoding 14. Flash Presence Detect 41 Encoding 15. BCSR3 Description Engineering 16. EXTOOLI03 Assignment17. External Tool Revision Encoding 18. ADS Revision Encoding PPC Bus Memory Map MSC8101ADS Memory Map FF800000 Ffffffff MSC8101ADS Memory MapFE000000 Ffffffff FF000000 Ffffffff ADS Power Scheme Power rails 713 5V Bus Off-Board Application Maximum Current Consumption711 5V Bus 712 3V Bus Appendix a MSC8101 Bill of Material Table A-1. MSC8101ADS Bill Of Material A1 BOM Freescale Inc Inc Dale Freescale Semiconductor Freescale Semiconductor, Inc Appendix B Support Information B11 Interconnect Signals Table B1-2. P1 System Expansion Interconnect Signals TSTAT2 TSTAT3 TSTAT4 TSTAT5 GNDTSTAT0 TSTAT1 Damage to the PM5350 ATM UNI Clkx EXPD3 EXPD0EXPD1 EXPD2 EXPCTL0 Table B1-3. P2 CPM Expansion Interconnect Signals B12 MSC8101ADS’s P2 CPM Expansion ConnectorSCC1RXD PD30 PD7 SPICLKPD18SPIMOSIPD17 Hwrds Atmrca PA26 Atmtsoc PA29Atmrsoc PA27 Atmrfclk ATMRXD4 PA14 ATMRXD7 PA17ATMRXD6 PA16 ATMRXD5 PA15 Fethcrs PB26 Fethtxen PB29Fethrxer PB28 Fethcol PB27 HD3 HD0HD1 HD2 Fethmdc PC13 Atmfclk PC26 SMCTX1PC5 Fethmdio PC12PC7 PC6 Table B1-4. P3 ISP Connector Interconnect Signals B14 P4 Host Interface ConnectorB13 Hreq HD1 HD2 HD3 HD4 HD5 HD6 HD7 HD8 HD9HA1 HA2 HA3 HCS1 Hack HDS Table B1-6. P6 JTAG/ONCE Connector Interconnect SignalsB15 P5, P7, P8, P9, P10, P13, P14 Logic Analyzer Connectors B16 B19 P17,P18 Double RJ45 T1/E1 Line Connectors Table B1-7. P12 Ethernet Port Interconnect SignalsB17 P12 Ethernet Port Connector B18 P15,P16 SMB Connectors B111 P20,P22,P23,P25 RCA Jack Connectors B110 P19,P21,P24 Stereo Phone Jack Connectors B113 P27A,B RS232 Ports’ Connectors Table B1-10. P27A Interconnect SignalsTable B1-11. P27B Interconnect Signals B112 P26 5V Power Supply Connectors Freescale Semiconductor, Inc Appendix C Program Information Freescale Semiconductor, Inc C11 First Include File Logic Equations C12 Second Include file C13 Main File Constant Constant SHIFTLENGTH= Length of HRD/HRW Delay Shifter SIZE0Constant EE45HOLDVALUE Constant SIZE1 HRESET~ Bidir Constant TCPCDEFAULT0 Constant TCPCDEFAULT1HDIMDEN~ Host SW Enable RSTCNF~ Output SRESET~ HRRQEN~ SBOOTENOUT~SPARE1 Output HDIEN~ WDTIMER4 WDTIMER1WDTIMER2 WDTIMER3 Scndcfgbyteread Thirdcfgbyteread Fourthcfgbyteread EepromenableResets Cleartowdctrl BCSR1 SBOOTEN~ BCSR3PONDEF0..SIZE3 BCSR3IRQ0 BCSR1PONDEF0..SIZE1 Begin Defaults END DefaultsBCSR0 BCSR0PONCONST0..5 EEDPONDEFAULT,RSV37PONDEFAULT ElseEND if END Generate END if EE PinsRegularpoweronreset = RPORI~ == Regularponresetactive PSDVAL~ = Opndrnvcc END if Else If Hdds thenIf !HDSP then Hdiwr = Else Hdiwr = Elsif MPCWRITEBCSR6 then Elsif MPCWRITEBCSR1 thenElsif MPCWRITEBCSR4 then Elsif MPCWRITEBCSR5 then SIGNALLAMP1~ Elsif MPCREADBCSR1 then If MPCREADBCSR0 thenElsif MPCREADBCSR3 then Elsif Scndcfgbyteread then HRESET~ =SRESET~ = Elsif Firstcfgbyteread then END if If !T1234EN~ & FETHIEN~ then Then SIGLAMP0OUT~ = GND ElseThen SIGLAMP1OUT~ Else SIGLAMP1OUT~ 116 END if Drive Poreset Impulse Reconfig Using BCSR4 Watchdog for Auto ReconfigurationMODCK1-3 Driven 118