MSC8101 ADS
MSC8101ADS RevB User’s Manual
Contents
ATM on LD14
BOM
Freescale Semiconductor, Inc
List of Figures
Viii
List of Tables
Freescale Semiconductor, Inc
Abbreviations’ List
Introduction
Related Documentation
MSC8101ADS Specifications
Specification
Characteristics Specifications
ADS Features
Freescale Semiconductor, Inc
Semiconductor, Inc
Hardware Preparation
MSC8101ADS Top Side Part Location diagram
Setting MODCK13 For Initial PLLs’ Multiplication Factor SW9
Setting The Core Supply Voltage Level
Setting HReset Configuration Source
OnCE Connection Scheme
Host I/F Operation
Stand Alone Operation
Host System Debug Scheme B
34 +5V Power Supply Connection
JTAG/OnCE Connector P6
Host I/F Connector P4
P6 JTAG/OnCE Port Connector
P4 Host I/F Connector
Terminal to MSC8101ADS RS-232 Connection
Flash Memory Simm Installation
38 10/100-Base-T Ethernet Port Connection
Flash Memory Simm Insertion
Host I/F Setting SW1
Emulator Enable EE SW2
Soft Reset Sreset Switch SW4
Abort Switch SW3
Data Bus Width Setting SW5 & SW6
Power-On Reset Switch Preset SW8
Hard Reset Hreset Switch SW7
Configuration Switch SW9
Modck
Available Clock Mode Setting
Boot Mode Select SW10
CPM
Jumpers
Software Options Switch SW11
431 JP1 DLL Disable
432 JP2 Clock Buffer Set
437 JP9 5V power supply for Codec
433 JP3 50 Ohm Enable
436 JP6,JP7 MIC Enable
434 JP4 VPP Source Selector
LEDs
ATM RX Indicator LD6
Ethernet Link Indicator LD4
Fast Ethernet Clsn Indicator LD5
ATM TX Indicator LD7
MSC8101’s Registers’ Programming
System Initialization
SIU Registers’ Programming
Memory Controller Registers Programming
Memory Controller Initialization for 10050a MHz
Memory Controller Initialization for 10050a MHz
Mbmr
Power On Reset Configuration
Reset & Reset Configuration
Power- On Reset
Manual Hard Reset
Summary Reset Configuration Schemes
Hard Reset Configuration Word
Manual Soft Reset
IRQ2
Local Interrupter
Clock Generator
Bus Buffering
Chip Select Generator
Synchronous Dram Bank
MSC8101ADS Chip Select Assignments Bus Timing Machine
Sdram Programming
MHz Sdram Mode Register Programming
Sdram
Flash Memory Simm
Cycle Type \ Flash Delay nsec
Sdram Refresh
Flash Simm Connection Scheme
Flash Programming Voltage
Communication Ports
Ports Function Enable
MSC8101 I/O Ports/Name
581 ATM Port
582 100/10 Base T Port
Audio Codec
CS4221 Programming
5831 CS4221 Programming
584 T1/E1 Ports
CS4221 Programming
585 RS232 Ports
Host I/F
DMA off-board tool
Host I/F Interconnect signals
Board Control & Status Register Bcsr
BIT Mnemonic
BCSR0 Description
BCSR0 Board Control / Status Register
PON ATT DEF Hostcsp
10. BCSR1 Description
BCSR0 Description
BCSR1 Board Control / Status Register
Fethien
10. BCSR1 Description
PON ATT DEF Atmrst
Fethrst
12. BCSR2 Description
11. Peripheral’s Availability Decoding
BCSR2 Board Control / Status Register
14. Flash Presence Detect 41 Encoding
12. BCSR2 Description
13. Flash Presence Detect 75 Encoding
BCSR3 Board Status Register
15. BCSR3 Description
18. ADS Revision Encoding
16. EXTOOLI03 Assignment
17. External Tool Revision Encoding
Engineering
PPC Bus Memory Map
MSC8101ADS Memory Map
FF000000 Ffffffff
MSC8101ADS Memory Map
FE000000 Ffffffff
FF800000 Ffffffff
Power rails
ADS Power Scheme
712 3V Bus
Off-Board Application Maximum Current Consumption
711 5V Bus
713 5V Bus
Appendix a MSC8101 Bill of Material
A1 BOM
Table A-1. MSC8101ADS Bill Of Material
Freescale
Inc
Inc
Dale
Freescale
Semiconductor
Freescale Semiconductor, Inc
Appendix B Support Information
Interconnect Signals
B11
Table B1-2. P1 System Expansion Interconnect Signals
TSTAT1
GND
TSTAT0
TSTAT2 TSTAT3 TSTAT4 TSTAT5
Clkx
Damage to the PM5350 ATM UNI
EXPD2
EXPD0
EXPD1
EXPD3
EXPCTL0
B12 MSC8101ADS’s P2 CPM Expansion Connector
Table B1-3. P2 CPM Expansion Interconnect Signals
SCC1RXD PD30
Hwrds
SPICLKPD18
SPIMOSIPD17
PD7
Atmrfclk
Atmtsoc PA29
Atmrsoc PA27
Atmrca PA26
ATMRXD5 PA15
ATMRXD7 PA17
ATMRXD6 PA16
ATMRXD4 PA14
Fethcol PB27
Fethtxen PB29
Fethrxer PB28
Fethcrs PB26
HD2
HD0
HD1
HD3
Atmfclk PC26
Fethmdc PC13
PC6
Fethmdio PC12
PC7
SMCTX1PC5
B14 P4 Host Interface Connector
Table B1-4. P3 ISP Connector Interconnect Signals
B13
Hack
HD1 HD2 HD3 HD4 HD5 HD6 HD7 HD8 HD9
HA1 HA2 HA3 HCS1
Hreq
B16
Table B1-6. P6 JTAG/ONCE Connector Interconnect Signals
B15 P5, P7, P8, P9, P10, P13, P14 Logic Analyzer Connectors
HDS
B18 P15,P16 SMB Connectors
Table B1-7. P12 Ethernet Port Interconnect Signals
B17 P12 Ethernet Port Connector
B19 P17,P18 Double RJ45 T1/E1 Line Connectors
B110 P19,P21,P24 Stereo Phone Jack Connectors
B111 P20,P22,P23,P25 RCA Jack Connectors
B112 P26 5V Power Supply Connectors
Table B1-10. P27A Interconnect Signals
Table B1-11. P27B Interconnect Signals
B113 P27A,B RS232 Ports’ Connectors
Freescale Semiconductor, Inc
Appendix C Program Information
Freescale Semiconductor, Inc
Logic Equations
C11 First Include File
C12 Second Include file
C13 Main File
Constant SIZE1
Constant SHIFTLENGTH= Length of HRD/HRW Delay Shifter SIZE0
Constant EE45HOLDVALUE
Constant
SRESET~
Constant TCPCDEFAULT0 Constant TCPCDEFAULT1
HDIMDEN~ Host SW Enable RSTCNF~ Output
HRESET~ Bidir
HDIEN~
SBOOTENOUT~
SPARE1 Output
HRRQEN~
WDTIMER3
WDTIMER1
WDTIMER2
WDTIMER4
BCSR1 SBOOTEN~
Eepromenable
Resets Cleartowdctrl
Scndcfgbyteread Thirdcfgbyteread Fourthcfgbyteread
BCSR1PONDEF0..SIZE1
BCSR3
IRQ0
BCSR3PONDEF0..SIZE3
END Defaults
Begin Defaults
BCSR0 BCSR0PONCONST0..5
Else
EEDPONDEFAULT,RSV37PONDEFAULT
END if END Generate
PSDVAL~ = Opndrnvcc
EE Pins
Regularpoweronreset = RPORI~ == Regularponresetactive
END if
Else Hdiwr =
If Hdds then
If !HDSP then Hdiwr =
END if Else
Elsif MPCWRITEBCSR5 then
Elsif MPCWRITEBCSR1 then
Elsif MPCWRITEBCSR4 then
Elsif MPCWRITEBCSR6 then
If MPCREADBCSR0 then
SIGNALLAMP1~ Elsif MPCREADBCSR1 then
Elsif MPCREADBCSR3 then
Elsif Firstcfgbyteread then
HRESET~ =
SRESET~ =
Elsif Scndcfgbyteread then
Else SIGLAMP1OUT~
Then SIGLAMP0OUT~ = GND Else
Then SIGLAMP1OUT~
END if If !T1234EN~ & FETHIEN~ then
116
Watchdog for Auto Reconfiguration
END if Drive Poreset Impulse Reconfig Using BCSR4
MODCK1-3 Driven
118