Appendix B Support Information | Nortel Networks MSC8101 ADS

Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.

APPENDIX B - Support Information

MOTOROLA

MSC8101ADS RevB User’s Manual

B-75

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Nortel Networks MSC8101 ADS user manual Appendix B Support Information

Contents

MSC8101 ADS MSC8101ADS RevB User’s Manual Contents ATM on LD14 BOM Freescale Semiconductor, Inc List of Figures Viii List of Tables Freescale Semiconductor, Inc Abbreviations’ List IntroductionRelated Documentation MSC8101ADS Specifications SpecificationCharacteristics Specifications ADS Features Freescale Semiconductor, Inc Semiconductor, Inc Hardware Preparation MSC8101ADS Top Side Part Location diagram Setting MODCK13 For Initial PLLs’ Multiplication Factor SW9 Setting The Core Supply Voltage LevelSetting HReset Configuration Source OnCE Connection Scheme Host I/F Operation Stand Alone Operation Host System Debug Scheme B 34 +5V Power Supply Connection JTAG/OnCE Connector P6 Host I/F Connector P4 P6 JTAG/OnCE Port Connector P4 Host I/F Connector Terminal to MSC8101ADS RS-232 Connection Flash Memory Simm Installation 38 10/100-Base-T Ethernet Port Connection Flash Memory Simm Insertion Host I/F Setting SW1 Emulator Enable EE SW2 Soft Reset Sreset Switch SW4 Abort Switch SW3Data Bus Width Setting SW5 & SW6 Power-On Reset Switch Preset SW8 Hard Reset Hreset Switch SW7Configuration Switch SW9 Available Clock Mode Setting Boot Mode Select SW10Modck CPM Software Options Switch SW11 431 JP1 DLL DisableJumpers 432 JP2 Clock Buffer Set 433 JP3 50 Ohm Enable 436 JP6,JP7 MIC Enable437 JP9 5V power supply for Codec 434 JP4 VPP Source Selector LEDs Ethernet Link Indicator LD4 Fast Ethernet Clsn Indicator LD5ATM RX Indicator LD6 ATM TX Indicator LD7 MSC8101’s Registers’ Programming System Initialization SIU Registers’ ProgrammingMemory Controller Registers Programming Memory Controller Initialization for 10050a MHz Memory Controller Initialization for 10050a MHz Mbmr Reset & Reset Configuration Power- On ResetPower On Reset Configuration Manual Hard Reset Summary Reset Configuration Schemes Hard Reset Configuration Word Manual Soft Reset IRQ2 Local Interrupter Clock Generator Bus Buffering Chip Select Generator Synchronous Dram Bank MSC8101ADS Chip Select Assignments Bus Timing Machine Sdram Programming MHz Sdram Mode Register ProgrammingSdram Flash Memory Simm Cycle Type \ Flash Delay nsecSdram Refresh Flash Simm Connection Scheme Flash Programming Voltage Communication Ports Ports Function Enable MSC8101 I/O Ports/Name 581 ATM Port 582 100/10 Base T Port Audio Codec CS4221 Programming5831 CS4221 Programming 584 T1/E1 Ports CS4221 Programming585 RS232 Ports Host I/F DMA off-board tool Host I/F Interconnect signalsBoard Control & Status Register Bcsr BCSR0 Description BCSR0 Board Control / Status RegisterBIT Mnemonic PON ATT DEF Hostcsp 10. BCSR1 Description BCSR0 DescriptionBCSR1 Board Control / Status Register 10. BCSR1 Description PON ATT DEF AtmrstFethien Fethrst 12. BCSR2 Description 11. Peripheral’s Availability DecodingBCSR2 Board Control / Status Register 12. BCSR2 Description 13. Flash Presence Detect 75 Encoding14. Flash Presence Detect 41 Encoding BCSR3 Board Status Register 15. BCSR3 Description 16. EXTOOLI03 Assignment 17. External Tool Revision Encoding18. ADS Revision Encoding Engineering PPC Bus Memory Map MSC8101ADS Memory Map MSC8101ADS Memory Map FE000000 FfffffffFF000000 Ffffffff FF800000 Ffffffff Power rails ADS Power Scheme Off-Board Application Maximum Current Consumption 711 5V Bus712 3V Bus 713 5V Bus Appendix a MSC8101 Bill of Material A1 BOM Table A-1. MSC8101ADS Bill Of Material Freescale Inc Inc Dale Freescale Semiconductor Freescale Semiconductor, Inc Appendix B Support Information Interconnect Signals B11 Table B1-2. P1 System Expansion Interconnect Signals GND TSTAT0TSTAT1 TSTAT2 TSTAT3 TSTAT4 TSTAT5 Clkx Damage to the PM5350 ATM UNI EXPD0 EXPD1EXPD2 EXPD3 EXPCTL0 B12 MSC8101ADS’s P2 CPM Expansion Connector Table B1-3. P2 CPM Expansion Interconnect SignalsSCC1RXD PD30 SPICLKPD18 SPIMOSIPD17Hwrds PD7 Atmtsoc PA29 Atmrsoc PA27Atmrfclk Atmrca PA26 ATMRXD7 PA17 ATMRXD6 PA16ATMRXD5 PA15 ATMRXD4 PA14 Fethtxen PB29 Fethrxer PB28Fethcol PB27 Fethcrs PB26 HD0 HD1HD2 HD3 Atmfclk PC26 Fethmdc PC13 Fethmdio PC12 PC7PC6 SMCTX1PC5 B14 P4 Host Interface Connector Table B1-4. P3 ISP Connector Interconnect SignalsB13 HD1 HD2 HD3 HD4 HD5 HD6 HD7 HD8 HD9 HA1 HA2 HA3 HCS1Hack Hreq Table B1-6. P6 JTAG/ONCE Connector Interconnect Signals B15 P5, P7, P8, P9, P10, P13, P14 Logic Analyzer ConnectorsB16 HDS Table B1-7. P12 Ethernet Port Interconnect Signals B17 P12 Ethernet Port ConnectorB18 P15,P16 SMB Connectors B19 P17,P18 Double RJ45 T1/E1 Line Connectors B110 P19,P21,P24 Stereo Phone Jack Connectors B111 P20,P22,P23,P25 RCA Jack Connectors Table B1-10. P27A Interconnect Signals Table B1-11. P27B Interconnect SignalsB112 P26 5V Power Supply Connectors B113 P27A,B RS232 Ports’ Connectors Freescale Semiconductor, Inc Appendix C Program Information Freescale Semiconductor, Inc Logic Equations C11 First Include File C12 Second Include file C13 Main File Constant SHIFTLENGTH= Length of HRD/HRW Delay Shifter SIZE0 Constant EE45HOLDVALUEConstant SIZE1 Constant Constant TCPCDEFAULT0 Constant TCPCDEFAULT1 HDIMDEN~ Host SW Enable RSTCNF~ OutputSRESET~ HRESET~ Bidir SBOOTENOUT~ SPARE1 OutputHDIEN~ HRRQEN~ WDTIMER1 WDTIMER2WDTIMER3 WDTIMER4 Eepromenable Resets CleartowdctrlBCSR1 SBOOTEN~ Scndcfgbyteread Thirdcfgbyteread Fourthcfgbyteread BCSR3 IRQ0BCSR1PONDEF0..SIZE1 BCSR3PONDEF0..SIZE3 END Defaults Begin DefaultsBCSR0 BCSR0PONCONST0..5 Else EEDPONDEFAULT,RSV37PONDEFAULTEND if END Generate EE Pins Regularpoweronreset = RPORI~ == RegularponresetactivePSDVAL~ = Opndrnvcc END if If Hdds then If !HDSP then Hdiwr =Else Hdiwr = END if Else Elsif MPCWRITEBCSR1 then Elsif MPCWRITEBCSR4 thenElsif MPCWRITEBCSR5 then Elsif MPCWRITEBCSR6 then If MPCREADBCSR0 then SIGNALLAMP1~ Elsif MPCREADBCSR1 thenElsif MPCREADBCSR3 then HRESET~ = SRESET~ =Elsif Firstcfgbyteread then Elsif Scndcfgbyteread then Then SIGLAMP0OUT~ = GND Else Then SIGLAMP1OUT~Else SIGLAMP1OUT~ END if If !T1234EN~ & FETHIEN~ then 116 Watchdog for Auto Reconfiguration END if Drive Poreset Impulse Reconfig Using BCSR4MODCK1-3 Driven 118