Available Clock Mode Setting, Modck | Nortel Networks MSC8101 ADS

Freescale Semiconductor, Inc.

Operating Instructions

FIGURE 4-4 Switch SW9 MODCK - Description

Semiconductor, Inc.

HOST

CFG

FCFG

MODCK6

MODCK5

MODCK4

MODCK3

MODCK2

MODCK1

Set to ‘0’ <=

SW9

ON

8

7

6

5

4

3

2

1

=> Set to ’1’

Freescale

TABLE 4-1. Available Clock Mode Setting

		MODCK-				Clock	Clock In	CPM	PPC Bus	SC140 Core
						Clock	Clock In	CPM	PPC Bus	SC140 Core
-1	-2	-3	-4	-5	-6	Mode	MHz	MHz	MHz	MHz
-1	-2	-3	-4	-5	-6


0	0	1	1	1	1	57a	55	137.5	55a	275
0	0	1	0	0	1	9b	20	200	100	300

a. Factory setting.

b. Alternative clock mode for 100MHz bus frequency requires clock oscillator 20MHz

4•2•9 Boot Mode Select - SW10

SW10 is a 4-switch Dip-Switch with three poles in use. This switch selects Boot Mode over Altera FPGA on the Processor inputs EE0, EE4, EE5 during Power-On reset sequence. Setting SW10/1 (DBG) to ON brings holding EE0 at logic 1 during reset that puts the SC140 core into DEBUG MODE. In doing so BTM’s switch position will be ignored. See TABLE 5-1 on page 40 for more explanation. SW10 is factory set to all ON.

MOTOROLA

MSC8101ADS RevB User’s Manual

29

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Image 29

Nortel Networks MSC8101 ADS user manual Available Clock Mode Setting, Boot Mode Select SW10, Modck, Cpm

Contents

MSC8101 ADS MSC8101ADS RevB User’s Manual Contents ATM on LD14 BOM Freescale Semiconductor, Inc List of Figures Viii List of Tables Freescale Semiconductor, Inc Related Documentation IntroductionAbbreviations’ List Characteristics Specifications SpecificationMSC8101ADS Specifications ADS Features Freescale Semiconductor, Inc Semiconductor, Inc Hardware Preparation MSC8101ADS Top Side Part Location diagram Setting HReset Configuration Source Setting The Core Supply Voltage LevelSetting MODCK13 For Initial PLLs’ Multiplication Factor SW9 Host I/F Operation OnCE Connection Scheme Host System Debug Scheme B Stand Alone Operation JTAG/OnCE Connector P6 34 +5V Power Supply Connection P6 JTAG/OnCE Port Connector Host I/F Connector P4 Terminal to MSC8101ADS RS-232 Connection P4 Host I/F Connector 38 10/100-Base-T Ethernet Port Connection Flash Memory Simm Installation Flash Memory Simm Insertion Emulator Enable EE SW2 Host I/F Setting SW1 Data Bus Width Setting SW5 & SW6 Abort Switch SW3Soft Reset Sreset Switch SW4 Configuration Switch SW9 Hard Reset Hreset Switch SW7Power-On Reset Switch Preset SW8 Boot Mode Select SW10 Available Clock Mode SettingModck CPM 431 JP1 DLL Disable Software Options Switch SW11Jumpers 432 JP2 Clock Buffer Set 436 JP6,JP7 MIC Enable 433 JP3 50 Ohm Enable437 JP9 5V power supply for Codec 434 JP4 VPP Source Selector LEDs Fast Ethernet Clsn Indicator LD5 Ethernet Link Indicator LD4ATM RX Indicator LD6 ATM TX Indicator LD7 MSC8101’s Registers’ Programming Memory Controller Registers Programming SIU Registers’ ProgrammingSystem Initialization Memory Controller Initialization for 10050a MHz Memory Controller Initialization for 10050a MHz Mbmr Power- On Reset Reset & Reset ConfigurationPower On Reset Configuration Manual Hard Reset Hard Reset Configuration Word Summary Reset Configuration Schemes IRQ2 Manual Soft Reset Clock Generator Local Interrupter Chip Select Generator Bus Buffering MSC8101ADS Chip Select Assignments Bus Timing Machine Synchronous Dram Bank Sdram MHz Sdram Mode Register ProgrammingSdram Programming Sdram Refresh Cycle Type \ Flash Delay nsecFlash Memory Simm Flash Programming Voltage Flash Simm Connection Scheme Communication Ports MSC8101 I/O Ports/Name Ports Function Enable 582 100/10 Base T Port 581 ATM Port 5831 CS4221 Programming CS4221 ProgrammingAudio Codec 585 RS232 Ports CS4221 Programming584 T1/E1 Ports Host I/F Board Control & Status Register Bcsr Host I/F Interconnect signalsDMA off-board tool BCSR0 Board Control / Status Register BCSR0 DescriptionBIT Mnemonic PON ATT DEF Hostcsp BCSR1 Board Control / Status Register BCSR0 Description10. BCSR1 Description PON ATT DEF Atmrst 10. BCSR1 DescriptionFethien Fethrst BCSR2 Board Control / Status Register 11. Peripheral’s Availability Decoding12. BCSR2 Description 13. Flash Presence Detect 75 Encoding 12. BCSR2 Description14. Flash Presence Detect 41 Encoding BCSR3 Board Status Register 15. BCSR3 Description 17. External Tool Revision Encoding 16. EXTOOLI03 Assignment18. ADS Revision Encoding Engineering PPC Bus Memory Map MSC8101ADS Memory Map FE000000 Ffffffff MSC8101ADS Memory MapFF000000 Ffffffff FF800000 Ffffffff ADS Power Scheme Power rails 711 5V Bus Off-Board Application Maximum Current Consumption712 3V Bus 713 5V Bus Appendix a MSC8101 Bill of Material Table A-1. MSC8101ADS Bill Of Material A1 BOM Freescale Inc Inc Dale Freescale Semiconductor Freescale Semiconductor, Inc Appendix B Support Information B11 Interconnect Signals Table B1-2. P1 System Expansion Interconnect Signals TSTAT0 GNDTSTAT1 TSTAT2 TSTAT3 TSTAT4 TSTAT5 Damage to the PM5350 ATM UNI Clkx EXPD1 EXPD0EXPD2 EXPD3 EXPCTL0 SCC1RXD PD30 Table B1-3. P2 CPM Expansion Interconnect SignalsB12 MSC8101ADS’s P2 CPM Expansion Connector SPIMOSIPD17 SPICLKPD18Hwrds PD7 Atmrsoc PA27 Atmtsoc PA29Atmrfclk Atmrca PA26 ATMRXD6 PA16 ATMRXD7 PA17ATMRXD5 PA15 ATMRXD4 PA14 Fethrxer PB28 Fethtxen PB29Fethcol PB27 Fethcrs PB26 HD1 HD0HD2 HD3 Fethmdc PC13 Atmfclk PC26 PC7 Fethmdio PC12PC6 SMCTX1PC5 B13 Table B1-4. P3 ISP Connector Interconnect SignalsB14 P4 Host Interface Connector HA1 HA2 HA3 HCS1 HD1 HD2 HD3 HD4 HD5 HD6 HD7 HD8 HD9Hack Hreq B15 P5, P7, P8, P9, P10, P13, P14 Logic Analyzer Connectors Table B1-6. P6 JTAG/ONCE Connector Interconnect SignalsB16 HDS B17 P12 Ethernet Port Connector Table B1-7. P12 Ethernet Port Interconnect SignalsB18 P15,P16 SMB Connectors B19 P17,P18 Double RJ45 T1/E1 Line Connectors B111 P20,P22,P23,P25 RCA Jack Connectors B110 P19,P21,P24 Stereo Phone Jack Connectors Table B1-11. P27B Interconnect Signals Table B1-10. P27A Interconnect SignalsB112 P26 5V Power Supply Connectors B113 P27A,B RS232 Ports’ Connectors Freescale Semiconductor, Inc Appendix C Program Information Freescale Semiconductor, Inc C11 First Include File Logic Equations C12 Second Include file C13 Main File Constant EE45HOLDVALUE Constant SHIFTLENGTH= Length of HRD/HRW Delay Shifter SIZE0Constant SIZE1 Constant HDIMDEN~ Host SW Enable RSTCNF~ Output Constant TCPCDEFAULT0 Constant TCPCDEFAULT1SRESET~ HRESET~ Bidir SPARE1 Output SBOOTENOUT~HDIEN~ HRRQEN~ WDTIMER2 WDTIMER1WDTIMER3 WDTIMER4 Resets Cleartowdctrl EepromenableBCSR1 SBOOTEN~ Scndcfgbyteread Thirdcfgbyteread Fourthcfgbyteread IRQ0 BCSR3BCSR1PONDEF0..SIZE1 BCSR3PONDEF0..SIZE3 BCSR0 BCSR0PONCONST0..5 Begin DefaultsEND Defaults END if END Generate EEDPONDEFAULT,RSV37PONDEFAULTElse Regularpoweronreset = RPORI~ == Regularponresetactive EE PinsPSDVAL~ = Opndrnvcc END if If !HDSP then Hdiwr = If Hdds thenElse Hdiwr = END if Else Elsif MPCWRITEBCSR4 then Elsif MPCWRITEBCSR1 thenElsif MPCWRITEBCSR5 then Elsif MPCWRITEBCSR6 then Elsif MPCREADBCSR3 then SIGNALLAMP1~ Elsif MPCREADBCSR1 thenIf MPCREADBCSR0 then SRESET~ = HRESET~ =Elsif Firstcfgbyteread then Elsif Scndcfgbyteread then Then SIGLAMP1OUT~ Then SIGLAMP0OUT~ = GND ElseElse SIGLAMP1OUT~ END if If !T1234EN~ & FETHIEN~ then 116 MODCK1-3 Driven END if Drive Poreset Impulse Reconfig Using BCSR4Watchdog for Auto Reconfiguration 118