Nortel Networks MSC8101 ADS user manual MHz Sdram Mode Register Programming, Sdram Programming

Freescale Semiconductor, Inc.

Functional Description

assigned to a CS line according to TABLE 5-3. "MSC8101ADS Chip Select Assignments" on page 44.

Address MUX

A29

A0

FIGURE 5-2 SDRAM Connection Scheme

			MT48LC2M32B2 x 2
CS2
	CS			CS
RAS
	RAS			RAS
CAS
	CAS			CAS
WE
		W			W
BNK1
	BA1			BA1

A28

A27

A1

BNK0 BA0 BA0

A(29:19)

A26

A20

A2

A3

	A(0:9)	A(9:0)	A(9:0)
	PSDA10
		A10	A10
3.3

A19

A9

CKE CKE

32

64

SYSCLK1	CLK	SYSCLK2	CLK
DQM(0:3)
	DQM(0:3)		DQM(0:3)
	DQ(31:0)		DQ(31:0)
D(0:31)
SDRAMEN64/32
DQM(4:7)
D(32:63)

Freescale Semiconductor, Inc.

5•6•1 SDRAM Programming

After power-up, SDRAM needs to be initialized by means of programming, to establish its mode of operation. The SDRAM is programmed by issuing a Mode Register Set command. During that command data is passed to the Mode Register through the SDRAM’s address lines. This command is fully supported by the SDRAM machine of the MSC8101.

Mode Register programming values are shown in TABLE 5-4. "100 MHz SDRAM Mode Register Programming" below:

TABLE 5-4. 100 MHz SDRAM Mode Register Programming

SDRAM	SDRAM Mode Reg	Value	Meaning:
Address Linea	Field
A10	Reserved	‘0’	Should program zero
A9	WB	‘0’	Read & Write Burst Access
A8, A7	Operation Mode	‘00’	Standard Operation
A6 - A4	CAS Latency	3/2b	CAS Latency
A3	Burst Type	‘0’	Sequential
A2 - A0 (LSB)	Burst Length	’010’/’011’c	4/8 Word Burst Length

a. Actually SDRAM’s A0 is connected to MSC8101 A29/A28 address line (32/64 bit width mode)

MOTOROLA MSC8101ADS RevB User’s Manual 45

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