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Nortel Networks MSC8101 ADS user manual Setting The Core Supply Voltage Level

Models: MSC8101 ADS

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Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.

Hardware Preparation

2•3•1 Setting The Core Supply Voltage Level

The internal Logic & PLL’s of the MSC8101 is powered separately through a supply bus named 1V5. The voltage level over this power bus may vary between 0.9V - 2.1V. In the lower voltage level, the Processor will operate at lower frequency range, consuming a smaller amount of power and vice-versa for the higher voltage level.

1V5 power level is factory set for 1.5V, but may be changed by RP2.

2•3•2 Setting MODCK(1:3) For Initial PLLs’ Multiplication Factor - SW9

During Power On reset sequence the Processor samples the three MODCK(1:3) lines which are driven by Altera FPGA device in accordance with SW9/1-3 setting. MODCK_HI field (MODCK[4– 6]), taken from the reset configuration word, are read from the Flash memory (default value from Altera FPGA for non-programmed Flash is read from SW9/4-6) or from Host Interface to establish with the multiplication factors of the CPM’s and Core’s PLLs. SW9 is shown in FIGURE 4-4 "Switch SW9 MODCK - Description" on page 29:

Some Clock Configuration can see in FIGURE 5-1 on page 43:

2•3•3 Setting HReset Configuration Source

The HReset Configuration WordA, read by the Processor while HRESET~ is asserted, may be taken from three sources:

1)Flash Memory SIMM.

2)Altera FPGA (Safe Mode).

3)Host I/F.

When SW9/7 is OFF, the Hard Reset Configuration Word is taken from Altera FPGA, when it is ON, the Hard Reset Configuration Word is taken from the Flash SIMM. If SW9/8 (Configuration) set OFF the Processor will be configured from Host, independent of SW9/7 (Flash Configuration Enable) position. For correct operation for Host Config. Mode Data bus width will be set to 32-bit wide.

A. In fact 8 Hard-Reset configuration words are read by a configuration master, however only the first is rel- evant for a single MSC8101.

18MSC8101ADS RevB User’s Manual MOTOROLA

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Nortel Networks MSC8101 ADS user manual Setting The Core Supply Voltage Level, Setting HReset Configuration Source

Contents

MSC8101 ADS MSC8101ADS RevB User’s Manual Contents ATM on LD14 BOM Freescale Semiconductor, Inc List of Figures Viii List of Tables Freescale Semiconductor, Inc Introduction Abbreviations’ ListRelated Documentation Specification MSC8101ADS SpecificationsCharacteristics Specifications ADS Features Freescale Semiconductor, Inc Semiconductor, Inc Hardware Preparation MSC8101ADS Top Side Part Location diagram Setting The Core Supply Voltage Level Setting MODCK13 For Initial PLLs’ Multiplication Factor SW9Setting HReset Configuration Source OnCE Connection Scheme Host I/F OperationStand Alone Operation Host System Debug Scheme B34 +5V Power Supply Connection JTAG/OnCE Connector P6Host I/F Connector P4 P6 JTAG/OnCE Port ConnectorP4 Host I/F Connector Terminal to MSC8101ADS RS-232 ConnectionFlash Memory Simm Installation 38 10/100-Base-T Ethernet Port ConnectionFlash Memory Simm Insertion Host I/F Setting SW1 Emulator Enable EE SW2Abort Switch SW3 Soft Reset Sreset Switch SW4Data Bus Width Setting SW5 & SW6 Hard Reset Hreset Switch SW7 Power-On Reset Switch Preset SW8Configuration Switch SW9 Modck Available Clock Mode SettingBoot Mode Select SW10 CPMJumpers Software Options Switch SW11431 JP1 DLL Disable 432 JP2 Clock Buffer Set437 JP9 5V power supply for Codec 433 JP3 50 Ohm Enable436 JP6,JP7 MIC Enable 434 JP4 VPP Source SelectorLEDs ATM RX Indicator LD6 Ethernet Link Indicator LD4Fast Ethernet Clsn Indicator LD5 ATM TX Indicator LD7MSC8101’s Registers’ Programming SIU Registers’ Programming System InitializationMemory Controller Registers Programming Memory Controller Initialization for 10050a MHz Memory Controller Initialization for 10050a MHz Mbmr Power On Reset Configuration Reset & Reset ConfigurationPower- On Reset Manual Hard ResetSummary Reset Configuration Schemes Hard Reset Configuration WordManual Soft Reset IRQ2Local Interrupter Clock GeneratorBus Buffering Chip Select GeneratorSynchronous Dram Bank MSC8101ADS Chip Select Assignments Bus Timing MachineMHz Sdram Mode Register Programming Sdram ProgrammingSdram Cycle Type \ Flash Delay nsec Flash Memory SimmSdram Refresh Flash Simm Connection Scheme Flash Programming VoltageCommunication Ports Ports Function Enable MSC8101 I/O Ports/Name581 ATM Port 582 100/10 Base T PortCS4221 Programming Audio Codec5831 CS4221 Programming CS4221 Programming 584 T1/E1 Ports585 RS232 Ports Host I/F Host I/F Interconnect signals DMA off-board toolBoard Control & Status Register Bcsr BIT Mnemonic BCSR0 DescriptionBCSR0 Board Control / Status Register PON ATT DEF HostcspBCSR0 Description 10. BCSR1 DescriptionBCSR1 Board Control / Status Register Fethien 10. BCSR1 DescriptionPON ATT DEF Atmrst Fethrst11. Peripheral’s Availability Decoding 12. BCSR2 DescriptionBCSR2 Board Control / Status Register 14. Flash Presence Detect 41 Encoding 12. BCSR2 Description13. Flash Presence Detect 75 Encoding BCSR3 Board Status Register15. BCSR3 Description 18. ADS Revision Encoding 16. EXTOOLI03 Assignment17. External Tool Revision Encoding EngineeringPPC Bus Memory Map MSC8101ADS Memory Map FF000000 Ffffffff MSC8101ADS Memory MapFE000000 Ffffffff FF800000 FfffffffPower rails ADS Power Scheme712 3V Bus Off-Board Application Maximum Current Consumption711 5V Bus 713 5V BusAppendix a MSC8101 Bill of Material A1 BOM Table A-1. MSC8101ADS Bill Of MaterialFreescale Inc Inc Dale Freescale Semiconductor Freescale Semiconductor, Inc Appendix B Support Information Interconnect Signals B11Table B1-2. P1 System Expansion Interconnect Signals TSTAT1 GNDTSTAT0 TSTAT2 TSTAT3 TSTAT4 TSTAT5Clkx Damage to the PM5350 ATM UNIEXPD2 EXPD0EXPD1 EXPD3EXPCTL0 Table B1-3. P2 CPM Expansion Interconnect Signals B12 MSC8101ADS’s P2 CPM Expansion ConnectorSCC1RXD PD30 Hwrds SPICLKPD18SPIMOSIPD17 PD7Atmrfclk Atmtsoc PA29Atmrsoc PA27 Atmrca PA26ATMRXD5 PA15 ATMRXD7 PA17ATMRXD6 PA16 ATMRXD4 PA14Fethcol PB27 Fethtxen PB29Fethrxer PB28 Fethcrs PB26HD2 HD0HD1 HD3Atmfclk PC26 Fethmdc PC13PC6 Fethmdio PC12PC7 SMCTX1PC5Table B1-4. P3 ISP Connector Interconnect Signals B14 P4 Host Interface ConnectorB13 Hack HD1 HD2 HD3 HD4 HD5 HD6 HD7 HD8 HD9HA1 HA2 HA3 HCS1 HreqB16 Table B1-6. P6 JTAG/ONCE Connector Interconnect SignalsB15 P5, P7, P8, P9, P10, P13, P14 Logic Analyzer Connectors HDSB18 P15,P16 SMB Connectors Table B1-7. P12 Ethernet Port Interconnect SignalsB17 P12 Ethernet Port Connector B19 P17,P18 Double RJ45 T1/E1 Line ConnectorsB110 P19,P21,P24 Stereo Phone Jack Connectors B111 P20,P22,P23,P25 RCA Jack ConnectorsB112 P26 5V Power Supply Connectors Table B1-10. P27A Interconnect SignalsTable B1-11. P27B Interconnect Signals B113 P27A,B RS232 Ports’ ConnectorsFreescale Semiconductor, Inc Appendix C Program Information Freescale Semiconductor, Inc Logic Equations C11 First Include FileC12 Second Include file C13 Main File Constant SIZE1 Constant SHIFTLENGTH= Length of HRD/HRW Delay Shifter SIZE0Constant EE45HOLDVALUE ConstantSRESET~ Constant TCPCDEFAULT0 Constant TCPCDEFAULT1HDIMDEN~ Host SW Enable RSTCNF~ Output HRESET~ BidirHDIEN~ SBOOTENOUT~SPARE1 Output HRRQEN~WDTIMER3 WDTIMER1WDTIMER2 WDTIMER4BCSR1 SBOOTEN~ EepromenableResets Cleartowdctrl Scndcfgbyteread Thirdcfgbyteread FourthcfgbytereadBCSR1PONDEF0..SIZE1 BCSR3IRQ0 BCSR3PONDEF0..SIZE3Begin Defaults END DefaultsBCSR0 BCSR0PONCONST0..5 EEDPONDEFAULT,RSV37PONDEFAULT ElseEND if END Generate PSDVAL~ = Opndrnvcc EE PinsRegularpoweronreset = RPORI~ == Regularponresetactive END ifElse Hdiwr = If Hdds thenIf !HDSP then Hdiwr = END if ElseElsif MPCWRITEBCSR5 then Elsif MPCWRITEBCSR1 thenElsif MPCWRITEBCSR4 then Elsif MPCWRITEBCSR6 thenSIGNALLAMP1~ Elsif MPCREADBCSR1 then If MPCREADBCSR0 thenElsif MPCREADBCSR3 then Elsif Firstcfgbyteread then HRESET~ =SRESET~ = Elsif Scndcfgbyteread thenElse SIGLAMP1OUT~ Then SIGLAMP0OUT~ = GND ElseThen SIGLAMP1OUT~ END if If !T1234EN~ & FETHIEN~ then116 END if Drive Poreset Impulse Reconfig Using BCSR4 Watchdog for Auto ReconfigurationMODCK1-3 Driven 118