OnCE Connection Scheme | Nortel Networks MSC8101 ADS guide

Freescale Semiconductor, Inc.

Freescale Semiconductor, Inc.

Installation Instructions

3 - Installation Instructions

The MSC8101ADS may be configured according to the required working environment as follows:

•Host Controlled Operation through OnCE Port

•Host Interface Operation through HDI16 Port

•Stand-Alone Mode

3•1 OnCE Connection Scheme

In this configuration the MSC8101ADS is controlled by a host computer via the OnCE Port, which is a subset of the JTAG port. This configuration allows for extensive debugging using on-host de- bugger. The host is connected to the ADS by a Command Converter provided by a third party (Macraigor Systems).

FIGURE 3-1 Host System Debug Scheme A

Host

Computer

					Command
	Media I/F				Converter
	Media I/F				Converter	14 Wire

Flat Cable

5V Power Supply

3•2 Host I/F Operation

In this configuration the MSC8101ADS is using HDI16 I/F that provide 16-bit wide, full-duplex, double-buffered, parallel port to connect directly to the data bus of a host processor. The HDI16 supports two classes of interfaces:

•Host processor/Microcontroller (MCU) connection interface

•DMA controller interface

A Host Device may be connected to the ADS via dedicated 36pin two rows header or via 128pin DIN - connector P2.

MOTOROLA

MSC8101ADS RevB User’s Manual

19

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Nortel Networks MSC8101 ADS user manual OnCE Connection Scheme, Host I/F Operation

Contents

MSC8101 ADS MSC8101ADS RevB User’s Manual Contents ATM on LD14 BOM Freescale Semiconductor, Inc List of Figures Viii List of Tables Freescale Semiconductor, Inc Abbreviations’ List IntroductionRelated Documentation MSC8101ADS Specifications SpecificationCharacteristics Specifications ADS Features Freescale Semiconductor, Inc Semiconductor, Inc Hardware Preparation MSC8101ADS Top Side Part Location diagram Setting MODCK13 For Initial PLLs’ Multiplication Factor SW9 Setting The Core Supply Voltage LevelSetting HReset Configuration Source Host I/F Operation OnCE Connection Scheme Host System Debug Scheme B Stand Alone Operation JTAG/OnCE Connector P6 34 +5V Power Supply Connection P6 JTAG/OnCE Port Connector Host I/F Connector P4 Terminal to MSC8101ADS RS-232 Connection P4 Host I/F Connector 38 10/100-Base-T Ethernet Port Connection Flash Memory Simm Installation Flash Memory Simm Insertion Emulator Enable EE SW2 Host I/F Setting SW1 Soft Reset Sreset Switch SW4 Abort Switch SW3Data Bus Width Setting SW5 & SW6 Power-On Reset Switch Preset SW8 Hard Reset Hreset Switch SW7Configuration Switch SW9 CPM Available Clock Mode SettingBoot Mode Select SW10 Modck 432 JP2 Clock Buffer Set Software Options Switch SW11431 JP1 DLL Disable Jumpers 434 JP4 VPP Source Selector 433 JP3 50 Ohm Enable436 JP6,JP7 MIC Enable 437 JP9 5V power supply for Codec LEDs ATM TX Indicator LD7 Ethernet Link Indicator LD4Fast Ethernet Clsn Indicator LD5 ATM RX Indicator LD6 MSC8101’s Registers’ Programming System Initialization SIU Registers’ ProgrammingMemory Controller Registers Programming Memory Controller Initialization for 10050a MHz Memory Controller Initialization for 10050a MHz Mbmr Manual Hard Reset Reset & Reset ConfigurationPower- On Reset Power On Reset Configuration Hard Reset Configuration Word Summary Reset Configuration Schemes IRQ2 Manual Soft Reset Clock Generator Local Interrupter Chip Select Generator Bus Buffering MSC8101ADS Chip Select Assignments Bus Timing Machine Synchronous Dram Bank Sdram Programming MHz Sdram Mode Register ProgrammingSdram Flash Memory Simm Cycle Type \ Flash Delay nsecSdram Refresh Flash Programming Voltage Flash Simm Connection Scheme Communication Ports MSC8101 I/O Ports/Name Ports Function Enable 582 100/10 Base T Port 581 ATM Port Audio Codec CS4221 Programming5831 CS4221 Programming 584 T1/E1 Ports CS4221 Programming585 RS232 Ports Host I/F DMA off-board tool Host I/F Interconnect signalsBoard Control & Status Register Bcsr PON ATT DEF Hostcsp BCSR0 DescriptionBCSR0 Board Control / Status Register BIT Mnemonic 10. BCSR1 Description BCSR0 DescriptionBCSR1 Board Control / Status Register Fethrst 10. BCSR1 DescriptionPON ATT DEF Atmrst Fethien 12. BCSR2 Description 11. Peripheral’s Availability DecodingBCSR2 Board Control / Status Register BCSR3 Board Status Register 12. BCSR2 Description13. Flash Presence Detect 75 Encoding 14. Flash Presence Detect 41 Encoding 15. BCSR3 Description Engineering 16. EXTOOLI03 Assignment17. External Tool Revision Encoding 18. ADS Revision Encoding PPC Bus Memory Map MSC8101ADS Memory Map FF800000 Ffffffff MSC8101ADS Memory MapFE000000 Ffffffff FF000000 Ffffffff ADS Power Scheme Power rails 713 5V Bus Off-Board Application Maximum Current Consumption711 5V Bus 712 3V Bus Appendix a MSC8101 Bill of Material Table A-1. MSC8101ADS Bill Of Material A1 BOM Freescale Inc Inc Dale Freescale Semiconductor Freescale Semiconductor, Inc Appendix B Support Information B11 Interconnect Signals Table B1-2. P1 System Expansion Interconnect Signals TSTAT2 TSTAT3 TSTAT4 TSTAT5 GNDTSTAT0 TSTAT1 Damage to the PM5350 ATM UNI Clkx EXPD3 EXPD0EXPD1 EXPD2 EXPCTL0 B12 MSC8101ADS’s P2 CPM Expansion Connector Table B1-3. P2 CPM Expansion Interconnect SignalsSCC1RXD PD30 PD7 SPICLKPD18SPIMOSIPD17 Hwrds Atmrca PA26 Atmtsoc PA29Atmrsoc PA27 Atmrfclk ATMRXD4 PA14 ATMRXD7 PA17ATMRXD6 PA16 ATMRXD5 PA15 Fethcrs PB26 Fethtxen PB29Fethrxer PB28 Fethcol PB27 HD3 HD0HD1 HD2 Fethmdc PC13 Atmfclk PC26 SMCTX1PC5 Fethmdio PC12PC7 PC6 B14 P4 Host Interface Connector Table B1-4. P3 ISP Connector Interconnect SignalsB13 Hreq HD1 HD2 HD3 HD4 HD5 HD6 HD7 HD8 HD9HA1 HA2 HA3 HCS1 Hack HDS Table B1-6. P6 JTAG/ONCE Connector Interconnect SignalsB15 P5, P7, P8, P9, P10, P13, P14 Logic Analyzer Connectors B16 B19 P17,P18 Double RJ45 T1/E1 Line Connectors Table B1-7. P12 Ethernet Port Interconnect SignalsB17 P12 Ethernet Port Connector B18 P15,P16 SMB Connectors B111 P20,P22,P23,P25 RCA Jack Connectors B110 P19,P21,P24 Stereo Phone Jack Connectors B113 P27A,B RS232 Ports’ Connectors Table B1-10. P27A Interconnect SignalsTable B1-11. P27B Interconnect Signals B112 P26 5V Power Supply Connectors Freescale Semiconductor, Inc Appendix C Program Information Freescale Semiconductor, Inc C11 First Include File Logic Equations C12 Second Include file C13 Main File Constant Constant SHIFTLENGTH= Length of HRD/HRW Delay Shifter SIZE0Constant EE45HOLDVALUE Constant SIZE1 HRESET~ Bidir Constant TCPCDEFAULT0 Constant TCPCDEFAULT1HDIMDEN~ Host SW Enable RSTCNF~ Output SRESET~ HRRQEN~ SBOOTENOUT~SPARE1 Output HDIEN~ WDTIMER4 WDTIMER1WDTIMER2 WDTIMER3 Scndcfgbyteread Thirdcfgbyteread Fourthcfgbyteread EepromenableResets Cleartowdctrl BCSR1 SBOOTEN~ BCSR3PONDEF0..SIZE3 BCSR3IRQ0 BCSR1PONDEF0..SIZE1 END Defaults Begin DefaultsBCSR0 BCSR0PONCONST0..5 Else EEDPONDEFAULT,RSV37PONDEFAULTEND if END Generate END if EE PinsRegularpoweronreset = RPORI~ == Regularponresetactive PSDVAL~ = Opndrnvcc END if Else If Hdds thenIf !HDSP then Hdiwr = Else Hdiwr = Elsif MPCWRITEBCSR6 then Elsif MPCWRITEBCSR1 thenElsif MPCWRITEBCSR4 then Elsif MPCWRITEBCSR5 then If MPCREADBCSR0 then SIGNALLAMP1~ Elsif MPCREADBCSR1 thenElsif MPCREADBCSR3 then Elsif Scndcfgbyteread then HRESET~ =SRESET~ = Elsif Firstcfgbyteread then END if If !T1234EN~ & FETHIEN~ then Then SIGLAMP0OUT~ = GND ElseThen SIGLAMP1OUT~ Else SIGLAMP1OUT~ 116 Watchdog for Auto Reconfiguration END if Drive Poreset Impulse Reconfig Using BCSR4MODCK1-3 Driven 118