BCSR2 Description | Nortel Networks MSC8101 ADS guide

Freescale Semiconductor, Inc.

			Freescale Semiconductor, Inc.
			Functional Description
			TABLE 5-12. BCSR2 Description

	BIT	MNEMONIC	Function	DEF	ATT.
	BIT	MNEMONIC	Function	SET	ATT.
				SET


	20 - 23	BREVN(0:3)	Board Revision Number (0:3). This field represents the revision code,	0	R
			hard-assigned to the ADS. See TABLE 5-18. "ADS Revision Encoding"
			on page 61, for revisions’ encoding.

	24	SWOPT2	Software Option 2. This is the LSB of the field. Shows the state of a	0	R
			dedicated dip-switch providing an option to manually change a program
			flow. For the setting of dip-switch see.

	25 - 27	FLASH_PD(7:5)	Flash Presence Detect(7:5). These lines are connected to the Flash SIMM	-	R
			presence detect lines, which encode the Delay of Flash SIMM mounted on
			the Flash SIMM socket. For the encoding of FLASH_PD(4:1) see TABLE
			5-13. "Flash Presence Detect (7:5) Encoding" on page 59.

	28 - 31	FLASH_PD(4:1)	Flash Presence Detect(4:1). These lines are connected to the Flash SIMM	-	R
			presence detect lines which encode the type of Flash SIMM mounted on the
			Flash SIMM socket. For the encoding of FLASH_PD(4:1) see TABLE 5-
			14. "Flash Presence Detect (4:1) Encoding" on page 59.

a. There is additional bit to this field. See bit 24 in the same table.

TABLE 5-13. Flash Presence Detect (7:5) Encoding

FLASH_PD(7:5)	FLASH DELAY [nsec]


000	Not Supported

001	150

010	100/120

011	80/90

100	70 nsec

101 - 111	Not Supported

TABLE 5-14. Flash Presence Detect (4:1) Encoding

FLASH_PD(4:1)	Flash TYPE / SIZE


0000	SM73288XG4JHBG0 - 32 MByte (4 banks of 4 X 2M X 8) by Smart Modular
	Technology.

0001	SM73248XG2JHBG0 - 16 MByte (2 banks of 4 X 2M X 8) by Smart Modular
	Technology.

0010	SM73228XG1JHBG0 - 8 MByte (1 bank of 4 X 2M X 8) by Smart Modular
	Technology.

0011 - 1111	Not Supported

5•11•4 BCSR3 - Board Status Register 3

BCSR3 is a status register which is accessed as word at offset C from the BCSR base address. Its a Read-Onlyregister. BCSR3’s various fields are described in TABLE 5-15. "BCSR3 Descrip-

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MSC8101ADS RevB User’s Manual

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Nortel Networks MSC8101 ADS BCSR2 Description, Flash Presence Detect 75 Encoding, Flash Presence Detect 41 Encoding

Contents

MSC8101 ADS MSC8101ADS RevB User’s Manual Contents ATM on LD14 BOM Freescale Semiconductor, Inc List of Figures Viii List of Tables Freescale Semiconductor, Inc Related Documentation IntroductionAbbreviations’ List Characteristics Specifications SpecificationMSC8101ADS Specifications ADS Features Freescale Semiconductor, Inc Semiconductor, Inc Hardware Preparation MSC8101ADS Top Side Part Location diagram Setting HReset Configuration Source Setting The Core Supply Voltage LevelSetting MODCK13 For Initial PLLs’ Multiplication Factor SW9 Host I/F Operation OnCE Connection Scheme Host System Debug Scheme B Stand Alone Operation JTAG/OnCE Connector P6 34 +5V Power Supply Connection P6 JTAG/OnCE Port Connector Host I/F Connector P4 Terminal to MSC8101ADS RS-232 Connection P4 Host I/F Connector 38 10/100-Base-T Ethernet Port Connection Flash Memory Simm Installation Flash Memory Simm Insertion Emulator Enable EE SW2 Host I/F Setting SW1 Data Bus Width Setting SW5 & SW6 Abort Switch SW3Soft Reset Sreset Switch SW4 Configuration Switch SW9 Hard Reset Hreset Switch SW7Power-On Reset Switch Preset SW8 CPM Available Clock Mode SettingBoot Mode Select SW10 Modck 432 JP2 Clock Buffer Set Software Options Switch SW11431 JP1 DLL Disable Jumpers 434 JP4 VPP Source Selector 433 JP3 50 Ohm Enable436 JP6,JP7 MIC Enable 437 JP9 5V power supply for Codec LEDs ATM TX Indicator LD7 Ethernet Link Indicator LD4Fast Ethernet Clsn Indicator LD5 ATM RX Indicator LD6 MSC8101’s Registers’ Programming Memory Controller Registers Programming SIU Registers’ ProgrammingSystem Initialization Memory Controller Initialization for 10050a MHz Memory Controller Initialization for 10050a MHz Mbmr Manual Hard Reset Reset & Reset ConfigurationPower- On Reset Power On Reset Configuration Hard Reset Configuration Word Summary Reset Configuration Schemes IRQ2 Manual Soft Reset Clock Generator Local Interrupter Chip Select Generator Bus Buffering MSC8101ADS Chip Select Assignments Bus Timing Machine Synchronous Dram Bank Sdram MHz Sdram Mode Register ProgrammingSdram Programming Sdram Refresh Cycle Type \ Flash Delay nsecFlash Memory Simm Flash Programming Voltage Flash Simm Connection Scheme Communication Ports MSC8101 I/O Ports/Name Ports Function Enable 582 100/10 Base T Port 581 ATM Port 5831 CS4221 Programming CS4221 ProgrammingAudio Codec 585 RS232 Ports CS4221 Programming584 T1/E1 Ports Host I/F Board Control & Status Register Bcsr Host I/F Interconnect signalsDMA off-board tool PON ATT DEF Hostcsp BCSR0 DescriptionBCSR0 Board Control / Status Register BIT Mnemonic BCSR1 Board Control / Status Register BCSR0 Description10. BCSR1 Description Fethrst 10. BCSR1 DescriptionPON ATT DEF Atmrst Fethien BCSR2 Board Control / Status Register 11. Peripheral’s Availability Decoding12. BCSR2 Description BCSR3 Board Status Register 12. BCSR2 Description13. Flash Presence Detect 75 Encoding 14. Flash Presence Detect 41 Encoding 15. BCSR3 Description Engineering 16. EXTOOLI03 Assignment17. External Tool Revision Encoding 18. ADS Revision Encoding PPC Bus Memory Map MSC8101ADS Memory Map FF800000 Ffffffff MSC8101ADS Memory MapFE000000 Ffffffff FF000000 Ffffffff ADS Power Scheme Power rails 713 5V Bus Off-Board Application Maximum Current Consumption711 5V Bus 712 3V Bus Appendix a MSC8101 Bill of Material Table A-1. MSC8101ADS Bill Of Material A1 BOM Freescale Inc Inc Dale Freescale Semiconductor Freescale Semiconductor, Inc Appendix B Support Information B11 Interconnect Signals Table B1-2. P1 System Expansion Interconnect Signals TSTAT2 TSTAT3 TSTAT4 TSTAT5 GNDTSTAT0 TSTAT1 Damage to the PM5350 ATM UNI Clkx EXPD3 EXPD0EXPD1 EXPD2 EXPCTL0 SCC1RXD PD30 Table B1-3. P2 CPM Expansion Interconnect SignalsB12 MSC8101ADS’s P2 CPM Expansion Connector PD7 SPICLKPD18SPIMOSIPD17 Hwrds Atmrca PA26 Atmtsoc PA29Atmrsoc PA27 Atmrfclk ATMRXD4 PA14 ATMRXD7 PA17ATMRXD6 PA16 ATMRXD5 PA15 Fethcrs PB26 Fethtxen PB29Fethrxer PB28 Fethcol PB27 HD3 HD0HD1 HD2 Fethmdc PC13 Atmfclk PC26 SMCTX1PC5 Fethmdio PC12PC7 PC6 B13 Table B1-4. P3 ISP Connector Interconnect SignalsB14 P4 Host Interface Connector Hreq HD1 HD2 HD3 HD4 HD5 HD6 HD7 HD8 HD9HA1 HA2 HA3 HCS1 Hack HDS Table B1-6. P6 JTAG/ONCE Connector Interconnect SignalsB15 P5, P7, P8, P9, P10, P13, P14 Logic Analyzer Connectors B16 B19 P17,P18 Double RJ45 T1/E1 Line Connectors Table B1-7. P12 Ethernet Port Interconnect SignalsB17 P12 Ethernet Port Connector B18 P15,P16 SMB Connectors B111 P20,P22,P23,P25 RCA Jack Connectors B110 P19,P21,P24 Stereo Phone Jack Connectors B113 P27A,B RS232 Ports’ Connectors Table B1-10. P27A Interconnect SignalsTable B1-11. P27B Interconnect Signals B112 P26 5V Power Supply Connectors Freescale Semiconductor, Inc Appendix C Program Information Freescale Semiconductor, Inc C11 First Include File Logic Equations C12 Second Include file C13 Main File Constant Constant SHIFTLENGTH= Length of HRD/HRW Delay Shifter SIZE0Constant EE45HOLDVALUE Constant SIZE1 HRESET~ Bidir Constant TCPCDEFAULT0 Constant TCPCDEFAULT1HDIMDEN~ Host SW Enable RSTCNF~ Output SRESET~ HRRQEN~ SBOOTENOUT~SPARE1 Output HDIEN~ WDTIMER4 WDTIMER1WDTIMER2 WDTIMER3 Scndcfgbyteread Thirdcfgbyteread Fourthcfgbyteread EepromenableResets Cleartowdctrl BCSR1 SBOOTEN~ BCSR3PONDEF0..SIZE3 BCSR3IRQ0 BCSR1PONDEF0..SIZE1 BCSR0 BCSR0PONCONST0..5 Begin DefaultsEND Defaults END if END Generate EEDPONDEFAULT,RSV37PONDEFAULTElse END if EE PinsRegularpoweronreset = RPORI~ == Regularponresetactive PSDVAL~ = Opndrnvcc END if Else If Hdds thenIf !HDSP then Hdiwr = Else Hdiwr = Elsif MPCWRITEBCSR6 then Elsif MPCWRITEBCSR1 thenElsif MPCWRITEBCSR4 then Elsif MPCWRITEBCSR5 then Elsif MPCREADBCSR3 then SIGNALLAMP1~ Elsif MPCREADBCSR1 thenIf MPCREADBCSR0 then Elsif Scndcfgbyteread then HRESET~ =SRESET~ = Elsif Firstcfgbyteread then END if If !T1234EN~ & FETHIEN~ then Then SIGLAMP0OUT~ = GND ElseThen SIGLAMP1OUT~ Else SIGLAMP1OUT~ 116 MODCK1-3 Driven END if Drive Poreset Impulse Reconfig Using BCSR4Watchdog for Auto Reconfiguration 118