3.5.3LPC Bus Interface
The LPC bus is a multiplexed (command, address, and data) serialized
LPC is designed to reduce the cost of traditional
The LPC is software transparent and does not require special drivers or configuration for its interface. The motherboard BIOS configures all devices at boot up. It has the ability to support a variable number of wait states, to have I/O and memory cycles retried in SMM handler and to support
The LPC bus provides system connectivity to the following devices:
■Redundant BIOS
■TPM
■IPMC
■
3.5.4Redundant BIOS
The Sun Netra CP3250 blade server provides redundant
The redundant Flash PROMs and SRAM devices are used by the BIOS. Each PROM is an 8 MB flash device. The primary flash device (FWH0) contains the primary BIOS image, factory default settings, and user configured settings. The primary BIOS chip is automatically selected for update during a firmware upgrade.
The secondary flash device (FWH1) contains a backup copy, normally of the last known good BIOS image, factory default settings, and last good
In the event of a checksum or other failure during boot of the primary BIOS image, the H8 switches the system over to the secondary device to allow system boot recovery.