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Toshiba TW40F80 manual Projection Television, TECHNICAL TRAINING MANUAL N5SS CHASSIS

Models: TW40F80

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NTDPJTV05

TECHNICAL TRAINING MANUAL N5SS CHASSIS

PROJECTION TELEVISION

TW40F80

Only the different points from the training manual “N5SS chassis” with its file No. 026-9506 are described on this manual.

For other parts common with “N5SS chassis”, please refer to the original manual with its file No. 026-9506.

TRAINING DEPARTMENT

1420-B TOSHIBA DRIVE LEBANON, TENNESSEE 37087 PHONE: (615)449-2360 FAX: (615)444-7520 www.toshiba.com/tacp

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Toshiba TW40F80 manual Projection Television, TECHNICAL TRAINING MANUAL N5SS CHASSIS

Contents

PROJECTION TELEVISION TW40F80TECHNICAL TRAINING MANUAL N5SS CHASSIS 9. REMOTE CONTROL CODE ASSIGNMENT ContentsSECTION IV DVD SWITCH CIRCUIT SECTION II TUNER, IF/MTS/S. PRO MODULE4. WIDE ASPECT CONVERSION CIRCUIT FAILURE ANALYSIS 5. TERMINAL FUNCTION, DESCRIPTION AND BLOCK DIAGRAM OF3. SYSTEM COMPONENT DIAGRAM OF DUAL UNIT SECTION VII 3-DIMENSION Y/C SEPARATOR CIRCUIT7. CONVERGENCE TROUBLESHOOTING CHART SECTION X DEFLECTION DISTORTION CORRECTION CIRCUIT1. DEFLECTION DISTORTION CORRECTION IC TA8859CP SECTION XI DIGITAL CONVERGENCE CIRCUITOUTLINE 2. MERITS OF BUS SYSTEM SECTION 1. FEATURE2-1. Improved Serviceability 2-2. Reduction of Parts CountC-Chassis 3. SPECIFICATIONSModel TW56F80 TW40F80Note No Owners manual page 4. FRONT VIEWIN-VIDEO 5. REAR VIEWTOSHIBA 6. REMOTE CONTROL VIEW6 DUAL 7. CHASSIS LAYOUTA517 8. CONSTRUCTION OF CHASSISBRT TBS 1-2. Major Features SECTION II TUNER, IF/MTS/S. PRO MODULE 1. CIRCUIT BLOCKFig. 2-1 Block diagram 1-1. OutlineSwitching Fig. 2-2 Block diagram of MVUS34S1-3. Audio Multiplex Demodulation Circuit Table 2-1 Matrix for broadcasting conditions and reception mode1-4. A.PRO Section Audio Processor Fig. 2-3 A.PRO block diagramMOTHER Configuration of the audio circuit and signal flow are given in FigVIDEO FRONT INPUT2-1. Outline 2. POP TUNERTerminal No Name1. OUTLINE OF CHANNEL SELECTION CIRCUIT SYSTEM SECTION III CHANNEL SELECTION CIRCUIT2. OPERATION OF CHANNEL SELECTION CIRCUIT 3. MICROCOMPUTER 4. MICROCOMPUTER TERMINAL FUNCTION Terminal Name MICROCOMPUTER TERMINAL NAME AND OPERATION LOGICFunction In/Out6. ON SCREEN FUNCTION 5. EEPROM QA027. SYSTEM BLOCK DIAGRAM Fig. 3-6 Local key assignment Table 3-1 Local key assignment 8. LOCAL KEY DETECTION METHODFunction FunctionCode 9. REMOTE CONTROL CODE ASSIGNMENTFunction to TV setCode Custom codes are 40-BFH TV set for North U.S.AFunction Custom codes are 40-BFH TV set for North U.S.AOPT0 9-1. Optional Setting for Each ModelOPT1 MODELS11. TEST SIGNAL SELECTION 10. ENTERING TO SERVICE MODE12. SERVICE ADJUSTMENT 13-1. Contents to be Confirmed by Customer 13. FAILURE DIAGNOSIS PROCEDURE13-3-1. Procedure Contents of self diagnosis13-4. Understanding Self Diagnosis Indication ContentsExample of screen display SELF CHECK13-4-1. Clearing method of self diagnosis result 13-4-2. Method utilizing inner signalVIDEO INPUT 1 terminal should be open 14-1. TV does Not Turned ON 14. TROUBLESHOOTING CHARTWhen remote unit key is pressed OK Replace QA01 Key on TV Voltage change at pins 17, 18 of QA01 5V to OK Replace QA01NG Check key-in circuit NG Check tuner power circuit No picture NG Voltage at pins of +5V, and OK14-5. No Indication On Screen 14-4. Memory Circuit CheckSECTION IV DVD SWITCH CIRCUIT 1. DVD SWITCH BLOCK DIAGRAM Open at Cb input Cb to DVD SW unit Cb input RV28 100k 2. OUTLINERV27 10k QV01 TA1218N2. CIRCUIT OPERATION SECTION V WAC CIRCUIT 1. OUTLINE2-1. Configuration 2-2-1. Signal FlowFig. 5-1 Wide aspect conversion unit block diagram PB6348 Fig. 5-2 Pin function of TC9097F QFP 80 pin Pin FunctionVDD5VCO2 Name Table 5-1 Names and functions of TC9097FFunction Function NameFig. 5-3 TC9097F system block diagram 3. BLOCK DIAGRAMName Function4. WIDE ASPECT CONVERSION CIRCUIT FAILURE ANALYSIS PROCEDURES 4-2. Raster Horizontal One 4-2-1. Adjustment Method1. OUTLINE SECTION VI DUAL CIRCUIT2. PRINCIPLES OF OPERATION 9-screen multi-search process3. SYSTEM COMPONENT DIAGRAM OF DUAL UNIT 4-1. Video/Color/Deflection Process Section 4. CIRCUIT OPERATIONSignalreception Fig. 6-3 Sub screen process section 4-2. Sub Screen Process SectionFig. 6-4 Main/Sub screen superimposing section 4-3. Main/Sub Screen Superimposing Section5. TERMINAL FUNCTION, DESCRIPTION AND BLOCK DIAGRAM OF MAIN ICdiagram QY01Fig. 6-6 QY01 mPC1832GT pin layout Power supply videoBlanking pulse output MULTIPLEX Fig. 6-7 QY03 TC9092AF internal block diagramPROGRAMDATA MEMORYADVREFY Fig. 6-8 QY03 TC9092AF pin layoutPin name Table 6-1 QY03 TC9092AF pin list NoPin function Pin name Table 6-2 QY03 TC9092AF pin list NoPin function Power supply +5V Fig. 6-9 QY10/QY11 M518221-30ZS internal block diagramFig. 6-10 QY10/QY11 M518221-30ZS pin layout Terminal name2. CIRCUIT DESCRIPTION SECTION VII 3-DIMENSION Y/C SEPARATOR CIRCUIT2-1. Configuration 1. OUTLINESignal name Fig. 7-1 3-dimension Y/C separator unit block diagramTerminal description PZ01 Voltage1-1. Theory of Operation SECTION VIII VERTICAL OUTPUT CIRCUIT 1. OUTLINE2-1. Actual Circuit 2. V OUTPUT CIRCUIT2-2. Sawtooth Waveform Generation 2-2-1. Circuit Operation2-3-1. Circuit Operation 2-3. V OutputFig. 8-7 Output stage power supply voltage 2-4. V Linearity Characteristic Correction 3. PROTECTION CIRCUIT FOR V DEFLECTION STOP2-4-1. S-character Correction Up-and Down-ward Extension Correction 2-4-2. Up-and Down-ward Linearity Balance3-1-1. Theory of Operation 3-1. +35V Over Current Protection Circuit4-1. Outline 4. RASTER POSITION SWITCHING CIRCUIT4-2. Operation 2. HORIZONTAL DRIVE CIRCUIT SECTION IX HORIZONTAL DEFLECTION CIRCUIT3. BASIC OPERATION OF HORIZONTAL DRIVE Fig. 9-1 H drive circuit block diagramOn period + ibOFF period current4-1. Theory of Operation 4. HORIZONTAL OUTPUT CIRCUIT4-1-1. Operation of Basic Circuit 2. t2 Description of the basic circuit 1. t1~t23. t2~t3 4. t3~t44-1-2. Linearity Correction LIN Amplitude Correction1 S-curve Correction S Capacitor Fig. 9-9 Linearity coil 2 Left-right Asymmetrical Correction LIN coil4-2-1. Outline 4-2. White Peak Bending Correction Circuit4-2-2. Operation Theory Fig. 9-11 White peak bending correction circuit4-3-1. Outline 4-3. H Blanking4-3-2. Theory of Operation 4-3-3. Circuit Operation4-4-1. Outline 4-4. 200V Low Voltage Protection4-4-2. Theory of Operation 5-1. Theory of Operation 5. HIGH VOLTAGE GENERATION CIRCUIT5-1-2. +35V 5-1-1. +210V5-1-3 5-1-4. High Voltage6-1. High Voltage Regulator 6. HIGH VOLTAGE CIRCUIT6-1-1. Outline Fig. 9-19 Basic circuit for high voltage regulatorFig. 9-22 Actual high voltage regulator circuit 6-1-3. Actual7-1. Outline 7. X-RAY PROTECTION CIRCUIT7-2. Operation Fig. 9-23 X-RAY protection circuit8-1. Outline 8. OVER CURRENT PROTECTION CIRCUIT8-2. Operation Fig. 9-24 Over current protection circuit1. DEFLECTION DISTORTION CORRECTION IC TA8859CP SECTION X DEFLECTION DISTORTION CORRECTION CIRCUIT SIDE DPC CIRCUIT1-2. Functions and Features Block Diagram2. DIODE MODULATOR CIRCUIT 3. ACTUAL CIRCUIT 3-1-1. Later Half Scanning Period 3-1. Basic Operation and Current Path3-1-2. First Half Scanning Period 3-1-4. First Half of Scanning Period 3-1-3. Later Half of Flyback Period2-1. Configuration SECTION XI DIGITAL CONVERGENCE CIRCUIT1. OUTLINE 2. CIRCUIT DESCRIPTION∗∗∗812bit8 Fig. 11-1 Block diagram3. PICTURE ADJUSTMENT 3-2-1. Outline 3-2. Service Mode3-2-2. Entering/Exiting Mode 1 First screen 3-2-3. Initial screen2 Second screen TOSHIBA 3-2-4. Key function of remote control unit3-3. Each Screen Adjustment Method 3-2-5. Operation procedure3-3-1. Normal/Full 3-3-2. Theater Wide1 3-3-3. Theater Wide 3-3-4. Theater Wide 4-1. When CRT is Replaced 4. CASE STUDY4-2. When Convergence Unit is Replaced 5-1. Adjusting Procedure in Replacing CRT 5. TROUBLESHOOTING5-2. Adjusting Procedure in Replacing Convergence Unit/Main Def 6-2-1. Signal flow 6. CONVERGENCE OUTPUT CIRCUIT4 To adjust from outside of digital convergence 6-1. Outline6-3. Convergence Block Diagram Vertical 7. CONVERGENCE TROUBLESHOOTING CHARTF BP WIDEVOLTAGEREG DV DH