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Toshiba TW40F80 manual Sub Screen Process Section, 3 Sub screen process section

Models: TW40F80

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4-2. Sub Screen Process Section

4-2. Sub Screen Process Section

The sub screen process section is shown in Fig. 6-3.

The Y, I and Q signals from the video/color/deflection pro- cess section are limited in their frequency bandwidth by the LPF in the prceeding stage and input to pins 6, 13 and 15 of QY03.

The frequency of 18.5 MHz generated by LY102 is multi- plied by 1/2 inside QY03. The Y signal is sampled by 9.25 MHz and the I and Q signals are sampled by 4.63 MHz (1/2 frequency to multiplex) and then the signals are converted into 8-bit digital signals.

The horizontal sync signal WHD (the signal mixed with WHD1 and WHD2 by QY43) for writing input to pins 21 and 20 of QY03 and the vertical sync signal WVD for trig- ger writing on the field memory QY10 and QY11.

The horizontal sync signal RHD for reading-out and the ver- tical sync signal RVD for reading out input to pins 75 and 77 of QY03 trigger the reading at 18.0 MHz which is created by 2/3-multiplying 27.0 MHz developed in LY101and then output as the analog signal.

The Y, I and Q signals converted for the sub screen are out- put from pins 95, 100 and 97 of QY03. The output signals are used for the input signals compressed by 1/2 in the hori- zontal direction in the double window mode and for the in- put signal compressed by 1/6 in the horizontal direction and by 1/3 in the vertical direction in 9-screen multi-search mode.

Then the signals are smoothed by the LPF in the next stage then input to the main/sub screen superimposing section.

Video/color/deflection process section

Signal reception circuit

				QY03 TC9092AF
			Sub screen process IC
Y	L.P.F	6	Y IN	Y OUT	95	L.P.F	Y

I	L.P.F	13	R-Y IN	R-Y OUT(I)	100	L.P.F	I

Q	L.P.F	15	B-Y IN	B-Y OUT(Q)	97	L.P.F	Q

I2C BUS (SCL, SDA)						79	SCL	YS OUT	70	YS
						79	SCL	YS OUT	70
						80	SDA			QY10, QY11
										QY10, QY11
										MSM518221-30ZS
WVD						20	FVS	MWD 0	48	2M
						20	FVS	MWD 0	48	memory
										memory
WHD2		1	OR		WHD					Date in
WHD2
				4		21	FHS		32
WHD1		2	circuit	4		21	FHS	MWD15
WHD1			circuit					MWD15

		QY43				24	OSCSI
		TC7S32F				25	OSCSO
						25	OSCSO
					LY102			MRD 0	51
					LY102
						77	FVM			Date out
								MRD15	65
PY01						75	FHM
PY01
	RVD					72	OSCMI
Y11	RVD					73	OSCMO
Y11						73	OSCMO
	RHD				LY101
Y12	RHD
Y12
Y01	YS
Y01

To Main/Sub pictore superimposing process section

Fig. 6-3 Sub screen process section

48

Image 48

Toshiba TW40F80 manual Sub Screen Process Section, 3 Sub screen process section

Contents

TW40F80 PROJECTION TELEVISIONTECHNICAL TRAINING MANUAL N5SS CHASSIS Contents 9. REMOTE CONTROL CODE ASSIGNMENTSECTION IV DVD SWITCH CIRCUIT SECTION II TUNER, IF/MTS/S. PRO MODULE5. TERMINAL FUNCTION, DESCRIPTION AND BLOCK DIAGRAM OF 4. WIDE ASPECT CONVERSION CIRCUIT FAILURE ANALYSIS3. SYSTEM COMPONENT DIAGRAM OF DUAL UNIT SECTION VII 3-DIMENSION Y/C SEPARATOR CIRCUITSECTION X DEFLECTION DISTORTION CORRECTION CIRCUIT 7. CONVERGENCE TROUBLESHOOTING CHART1. DEFLECTION DISTORTION CORRECTION IC TA8859CP SECTION XI DIGITAL CONVERGENCE CIRCUITSECTION 1. FEATURE OUTLINE 2. MERITS OF BUS SYSTEM2-1. Improved Serviceability 2-2. Reduction of Parts Count3. SPECIFICATIONS C-ChassisModel TW56F80 TW40F804. FRONT VIEW Note No Owners manual page5. REAR VIEW IN-VIDEO6. REMOTE CONTROL VIEW TOSHIBA7. CHASSIS LAYOUT 6 DUAL8. CONSTRUCTION OF CHASSIS A517BRT TBS SECTION II TUNER, IF/MTS/S. PRO MODULE 1. CIRCUIT BLOCK 1-2. Major FeaturesFig. 2-1 Block diagram 1-1. OutlineFig. 2-2 Block diagram of MVUS34S Switching1-3. Audio Multiplex Demodulation Circuit Table 2-1 Matrix for broadcasting conditions and reception modeFig. 2-3 A.PRO block diagram 1-4. A.PRO Section Audio ProcessorConfiguration of the audio circuit and signal flow are given in Fig MOTHERVIDEO FRONT INPUT2. POP TUNER 2-1. OutlineTerminal No NameSECTION III CHANNEL SELECTION CIRCUIT 1. OUTLINE OF CHANNEL SELECTION CIRCUIT SYSTEM2. OPERATION OF CHANNEL SELECTION CIRCUIT 3. MICROCOMPUTER 4. MICROCOMPUTER TERMINAL FUNCTION MICROCOMPUTER TERMINAL NAME AND OPERATION LOGIC Terminal NameFunction In/Out5. EEPROM QA02 6. ON SCREEN FUNCTION7. SYSTEM BLOCK DIAGRAM 8. LOCAL KEY DETECTION METHOD Fig. 3-6 Local key assignment Table 3-1 Local key assignmentFunction Function9. REMOTE CONTROL CODE ASSIGNMENT CodeFunction to TV setCustom codes are 40-BFH TV set for North U.S.A CodeFunction Custom codes are 40-BFH TV set for North U.S.A9-1. Optional Setting for Each Model OPT0OPT1 MODELS10. ENTERING TO SERVICE MODE 11. TEST SIGNAL SELECTION12. SERVICE ADJUSTMENT 13. FAILURE DIAGNOSIS PROCEDURE 13-1. Contents to be Confirmed by Customer13-3-1. Procedure Contents of self diagnosisContents 13-4. Understanding Self Diagnosis IndicationExample of screen display SELF CHECK13-4-2. Method utilizing inner signal 13-4-1. Clearing method of self diagnosis resultVIDEO INPUT 1 terminal should be open 14. TROUBLESHOOTING CHART 14-1. TV does Not Turned ONKey on TV Voltage change at pins 17, 18 of QA01 5V to OK Replace QA01 When remote unit key is pressed OK Replace QA01NG Check key-in circuit NG Check tuner power circuit No picture NG Voltage at pins of +5V, and OK14-4. Memory Circuit Check 14-5. No Indication On ScreenSECTION IV DVD SWITCH CIRCUIT 1. DVD SWITCH BLOCK DIAGRAM 2. OUTLINE Open at Cb input Cb to DVD SW unit Cb input RV28 100kRV27 10k QV01 TA1218NSECTION V WAC CIRCUIT 1. OUTLINE 2. CIRCUIT OPERATION2-1. Configuration 2-2-1. Signal FlowFig. 5-1 Wide aspect conversion unit block diagram PB6348 Pin Function Fig. 5-2 Pin function of TC9097F QFP 80 pinVDD5VCO2 Table 5-1 Names and functions of TC9097F NameFunction Name Function3. BLOCK DIAGRAM Fig. 5-3 TC9097F system block diagramName Function4. WIDE ASPECT CONVERSION CIRCUIT FAILURE ANALYSIS PROCEDURES 4-2-1. Adjustment Method 4-2. Raster Horizontal OneSECTION VI DUAL CIRCUIT 1. OUTLINE2. PRINCIPLES OF OPERATION 9-screen multi-search process3. SYSTEM COMPONENT DIAGRAM OF DUAL UNIT 4. CIRCUIT OPERATION 4-1. Video/Color/Deflection Process SectionSignalreception 4-2. Sub Screen Process Section Fig. 6-3 Sub screen process section4-3. Main/Sub Screen Superimposing Section Fig. 6-4 Main/Sub screen superimposing sectionMAIN IC 5. TERMINAL FUNCTION, DESCRIPTION AND BLOCK DIAGRAM OFdiagram QY01Power supply video Fig. 6-6 QY01 mPC1832GT pin layoutBlanking pulse output Fig. 6-7 QY03 TC9092AF internal block diagram MULTIPLEXPROGRAMDATA MEMORYFig. 6-8 QY03 TC9092AF pin layout ADVREFYTable 6-1 QY03 TC9092AF pin list No Pin namePin function Table 6-2 QY03 TC9092AF pin list No Pin namePin function Fig. 6-9 QY10/QY11 M518221-30ZS internal block diagram Power supply +5VFig. 6-10 QY10/QY11 M518221-30ZS pin layout Terminal nameSECTION VII 3-DIMENSION Y/C SEPARATOR CIRCUIT 2. CIRCUIT DESCRIPTION2-1. Configuration 1. OUTLINEFig. 7-1 3-dimension Y/C separator unit block diagram Signal nameTerminal description PZ01 VoltageSECTION VIII VERTICAL OUTPUT CIRCUIT 1. OUTLINE 1-1. Theory of Operation2. V OUTPUT CIRCUIT 2-1. Actual Circuit2-2. Sawtooth Waveform Generation 2-2-1. Circuit Operation2-3. V Output 2-3-1. Circuit OperationFig. 8-7 Output stage power supply voltage 3. PROTECTION CIRCUIT FOR V DEFLECTION STOP 2-4. V Linearity Characteristic Correction2-4-1. S-character Correction Up-and Down-ward Extension Correction 2-4-2. Up-and Down-ward Linearity Balance3-1. +35V Over Current Protection Circuit 3-1-1. Theory of Operation4. RASTER POSITION SWITCHING CIRCUIT 4-1. Outline4-2. Operation SECTION IX HORIZONTAL DEFLECTION CIRCUIT 2. HORIZONTAL DRIVE CIRCUIT3. BASIC OPERATION OF HORIZONTAL DRIVE Fig. 9-1 H drive circuit block diagram+ ib On periodOFF period current4. HORIZONTAL OUTPUT CIRCUIT 4-1. Theory of Operation4-1-1. Operation of Basic Circuit Description of the basic circuit 1. t1~t2 2. t23. t2~t3 4. t3~t4Amplitude Correction 4-1-2. Linearity Correction LIN1 S-curve Correction S Capacitor 2 Left-right Asymmetrical Correction LIN coil Fig. 9-9 Linearity coil4-2. White Peak Bending Correction Circuit 4-2-1. Outline4-2-2. Operation Theory Fig. 9-11 White peak bending correction circuit4-3. H Blanking 4-3-1. Outline4-3-2. Theory of Operation 4-3-3. Circuit Operation4-4. 200V Low Voltage Protection 4-4-1. Outline4-4-2. Theory of Operation 5. HIGH VOLTAGE GENERATION CIRCUIT 5-1. Theory of Operation5-1-1. +210V 5-1-2. +35V5-1-3 5-1-4. High Voltage6. HIGH VOLTAGE CIRCUIT 6-1. High Voltage Regulator6-1-1. Outline Fig. 9-19 Basic circuit for high voltage regulator6-1-3. Actual Fig. 9-22 Actual high voltage regulator circuit7. X-RAY PROTECTION CIRCUIT 7-1. Outline7-2. Operation Fig. 9-23 X-RAY protection circuit8. OVER CURRENT PROTECTION CIRCUIT 8-1. Outline8-2. Operation Fig. 9-24 Over current protection circuitSECTION X DEFLECTION DISTORTION CORRECTION CIRCUIT SIDE DPC CIRCUIT 1. DEFLECTION DISTORTION CORRECTION IC TA8859CP1-2. Functions and Features Block Diagram2. DIODE MODULATOR CIRCUIT 3. ACTUAL CIRCUIT 3-1. Basic Operation and Current Path 3-1-1. Later Half Scanning Period3-1-2. First Half Scanning Period 3-1-3. Later Half of Flyback Period 3-1-4. First Half of Scanning PeriodSECTION XI DIGITAL CONVERGENCE CIRCUIT 2-1. Configuration1. OUTLINE 2. CIRCUIT DESCRIPTIONFig. 11-1 Block diagram ∗∗∗812bit83. PICTURE ADJUSTMENT 3-2. Service Mode 3-2-1. Outline3-2-2. Entering/Exiting Mode 3-2-3. Initial screen 1 First screen2 Second screen 3-2-4. Key function of remote control unit TOSHIBA3-2-5. Operation procedure 3-3. Each Screen Adjustment Method3-3-1. Normal/Full 3-3-2. Theater Wide1 3-3-3. Theater Wide 3-3-4. Theater Wide 4. CASE STUDY 4-1. When CRT is Replaced4-2. When Convergence Unit is Replaced 5. TROUBLESHOOTING 5-1. Adjusting Procedure in Replacing CRT5-2. Adjusting Procedure in Replacing Convergence Unit/Main Def 6. CONVERGENCE OUTPUT CIRCUIT 6-2-1. Signal flow4 To adjust from outside of digital convergence 6-1. Outline6-3. Convergence Block Diagram 7. CONVERGENCE TROUBLESHOOTING CHART VerticalWIDE F BPVOLTAGEREG DV DH