Manuals / Toshiba / TV and Video / Projection Television

Toshiba TW40F80 manual Theater Wide

Models: TW40F80

1 101

Page 94

3-3-3. Theater Wide 2

298.9
256.2
128.1
Screen
center
0
128.1
256.2
298.9

435

362.5

217.5 40 inches 16:9 Screen

72.5

217.5

size: Horizontal 885mm x Vertical 498mm

362.5

435

Fig. 11-9

361.8
301.5
180.9
Screen
center
0
180.9
301.5
361.8

618

515

309

103

309

515

618

56 inches 16:9 Screen size: Horizontal 1239mm x Vertical 697mm

Fig. 11-10

Page 94

Image 94

Contents

PROJECTION TELEVISION TW40F80TECHNICAL TRAINING MANUAL N5SS CHASSIS SECTION IV DVD SWITCH CIRCUIT Contents9. REMOTE CONTROL CODE ASSIGNMENT SECTION II TUNER, IF/MTS/S. PRO MODULE3. SYSTEM COMPONENT DIAGRAM OF DUAL UNIT 5. TERMINAL FUNCTION, DESCRIPTION AND BLOCK DIAGRAM OF4. WIDE ASPECT CONVERSION CIRCUIT FAILURE ANALYSIS SECTION VII 3-DIMENSION Y/C SEPARATOR CIRCUIT1. DEFLECTION DISTORTION CORRECTION IC TA8859CP SECTION X DEFLECTION DISTORTION CORRECTION CIRCUIT7. CONVERGENCE TROUBLESHOOTING CHART SECTION XI DIGITAL CONVERGENCE CIRCUIT2-1. Improved Serviceability SECTION 1. FEATUREOUTLINE 2. MERITS OF BUS SYSTEM 2-2. Reduction of Parts CountModel 3. SPECIFICATIONSC-Chassis TW56F80 TW40F804. FRONT VIEW Note No Owners manual page5. REAR VIEW IN-VIDEO6. REMOTE CONTROL VIEW TOSHIBA7. CHASSIS LAYOUT 6 DUALA517 8. CONSTRUCTION OF CHASSISBRT TBS Fig. 2-1 Block diagram SECTION II TUNER, IF/MTS/S. PRO MODULE 1. CIRCUIT BLOCK1-2. Major Features 1-1. Outline1-3. Audio Multiplex Demodulation Circuit Fig. 2-2 Block diagram of MVUS34SSwitching Table 2-1 Matrix for broadcasting conditions and reception modeFig. 2-3 A.PRO block diagram 1-4. A.PRO Section Audio ProcessorVIDEO Configuration of the audio circuit and signal flow are given in FigMOTHER FRONT INPUTTerminal No 2. POP TUNER2-1. Outline Name1. OUTLINE OF CHANNEL SELECTION CIRCUIT SYSTEM SECTION III CHANNEL SELECTION CIRCUIT2. OPERATION OF CHANNEL SELECTION CIRCUIT 3. MICROCOMPUTER 4. MICROCOMPUTER TERMINAL FUNCTION Function MICROCOMPUTER TERMINAL NAME AND OPERATION LOGICTerminal Name In/Out5. EEPROM QA02 6. ON SCREEN FUNCTION7. SYSTEM BLOCK DIAGRAM Function 8. LOCAL KEY DETECTION METHODFig. 3-6 Local key assignment Table 3-1 Local key assignment FunctionFunction 9. REMOTE CONTROL CODE ASSIGNMENTCode to TV setFunction Custom codes are 40-BFH TV set for North U.S.ACode Custom codes are 40-BFH TV set for North U.S.AOPT1 9-1. Optional Setting for Each ModelOPT0 MODELS11. TEST SIGNAL SELECTION 10. ENTERING TO SERVICE MODE12. SERVICE ADJUSTMENT 13-3-1. Procedure 13. FAILURE DIAGNOSIS PROCEDURE13-1. Contents to be Confirmed by Customer Contents of self diagnosisExample of screen display Contents13-4. Understanding Self Diagnosis Indication SELF CHECK13-4-1. Clearing method of self diagnosis result 13-4-2. Method utilizing inner signalVIDEO INPUT 1 terminal should be open 14. TROUBLESHOOTING CHART 14-1. TV does Not Turned ONNG Check key-in circuit NG Check tuner power circuit Key on TV Voltage change at pins 17, 18 of QA01 5V to OK Replace QA01When remote unit key is pressed OK Replace QA01 No picture NG Voltage at pins of +5V, and OK14-4. Memory Circuit Check 14-5. No Indication On ScreenSECTION IV DVD SWITCH CIRCUIT 1. DVD SWITCH BLOCK DIAGRAM RV27 10k 2. OUTLINEOpen at Cb input Cb to DVD SW unit Cb input RV28 100k QV01 TA1218N2-1. Configuration SECTION V WAC CIRCUIT 1. OUTLINE2. CIRCUIT OPERATION 2-2-1. Signal FlowFig. 5-1 Wide aspect conversion unit block diagram PB6348 Fig. 5-2 Pin function of TC9097F QFP 80 pin Pin FunctionVDD5VCO2 Name Table 5-1 Names and functions of TC9097FFunction Name FunctionName 3. BLOCK DIAGRAMFig. 5-3 TC9097F system block diagram Function4. WIDE ASPECT CONVERSION CIRCUIT FAILURE ANALYSIS PROCEDURES 4-2-1. Adjustment Method 4-2. Raster Horizontal One2. PRINCIPLES OF OPERATION SECTION VI DUAL CIRCUIT1. OUTLINE 9-screen multi-search process3. SYSTEM COMPONENT DIAGRAM OF DUAL UNIT 4. CIRCUIT OPERATION 4-1. Video/Color/Deflection Process SectionSignalreception 4-2. Sub Screen Process Section Fig. 6-3 Sub screen process section4-3. Main/Sub Screen Superimposing Section Fig. 6-4 Main/Sub screen superimposing sectiondiagram MAIN IC5. TERMINAL FUNCTION, DESCRIPTION AND BLOCK DIAGRAM OF QY01Fig. 6-6 QY01 mPC1832GT pin layout Power supply videoBlanking pulse output PROGRAMDATA Fig. 6-7 QY03 TC9092AF internal block diagramMULTIPLEX MEMORYFig. 6-8 QY03 TC9092AF pin layout ADVREFYPin name Table 6-1 QY03 TC9092AF pin list NoPin function Pin name Table 6-2 QY03 TC9092AF pin list NoPin function Fig. 6-10 QY10/QY11 M518221-30ZS pin layout Fig. 6-9 QY10/QY11 M518221-30ZS internal block diagramPower supply +5V Terminal name2-1. Configuration SECTION VII 3-DIMENSION Y/C SEPARATOR CIRCUIT2. CIRCUIT DESCRIPTION 1. OUTLINETerminal description PZ01 Fig. 7-1 3-dimension Y/C separator unit block diagramSignal name VoltageSECTION VIII VERTICAL OUTPUT CIRCUIT 1. OUTLINE 1-1. Theory of Operation2-2. Sawtooth Waveform Generation 2. V OUTPUT CIRCUIT2-1. Actual Circuit 2-2-1. Circuit Operation2-3. V Output 2-3-1. Circuit OperationFig. 8-7 Output stage power supply voltage 2-4-1. S-character Correction Up-and Down-ward Extension Correction 3. PROTECTION CIRCUIT FOR V DEFLECTION STOP2-4. V Linearity Characteristic Correction 2-4-2. Up-and Down-ward Linearity Balance3-1. +35V Over Current Protection Circuit 3-1-1. Theory of Operation4-1. Outline 4. RASTER POSITION SWITCHING CIRCUIT4-2. Operation 3. BASIC OPERATION OF HORIZONTAL DRIVE SECTION IX HORIZONTAL DEFLECTION CIRCUIT2. HORIZONTAL DRIVE CIRCUIT Fig. 9-1 H drive circuit block diagramOFF period + ibOn period current4-1. Theory of Operation 4. HORIZONTAL OUTPUT CIRCUIT4-1-1. Operation of Basic Circuit 3. t2~t3 Description of the basic circuit 1. t1~t22. t2 4. t3~t44-1-2. Linearity Correction LIN Amplitude Correction1 S-curve Correction S Capacitor 2 Left-right Asymmetrical Correction LIN coil Fig. 9-9 Linearity coil4-2-2. Operation Theory 4-2. White Peak Bending Correction Circuit4-2-1. Outline Fig. 9-11 White peak bending correction circuit4-3-2. Theory of Operation 4-3. H Blanking4-3-1. Outline 4-3-3. Circuit Operation4-4-1. Outline 4-4. 200V Low Voltage Protection4-4-2. Theory of Operation 5. HIGH VOLTAGE GENERATION CIRCUIT 5-1. Theory of Operation5-1-3 5-1-1. +210V5-1-2. +35V 5-1-4. High Voltage6-1-1. Outline 6. HIGH VOLTAGE CIRCUIT6-1. High Voltage Regulator Fig. 9-19 Basic circuit for high voltage regulator6-1-3. Actual Fig. 9-22 Actual high voltage regulator circuit7-2. Operation 7. X-RAY PROTECTION CIRCUIT7-1. Outline Fig. 9-23 X-RAY protection circuit8-2. Operation 8. OVER CURRENT PROTECTION CIRCUIT8-1. Outline Fig. 9-24 Over current protection circuit1-2. Functions and Features SECTION X DEFLECTION DISTORTION CORRECTION CIRCUIT SIDE DPC CIRCUIT1. DEFLECTION DISTORTION CORRECTION IC TA8859CP Block Diagram2. DIODE MODULATOR CIRCUIT 3. ACTUAL CIRCUIT 3-1-1. Later Half Scanning Period 3-1. Basic Operation and Current Path3-1-2. First Half Scanning Period 3-1-3. Later Half of Flyback Period 3-1-4. First Half of Scanning Period1. OUTLINE SECTION XI DIGITAL CONVERGENCE CIRCUIT2-1. Configuration 2. CIRCUIT DESCRIPTIONFig. 11-1 Block diagram ∗∗∗812bit83. PICTURE ADJUSTMENT 3-2-1. Outline 3-2. Service Mode3-2-2. Entering/Exiting Mode 1 First screen 3-2-3. Initial screen2 Second screen 3-2-4. Key function of remote control unit TOSHIBA3-3. Each Screen Adjustment Method 3-2-5. Operation procedure3-3-1. Normal/Full 3-3-2. Theater Wide1 3-3-3. Theater Wide 3-3-4. Theater Wide 4-1. When CRT is Replaced 4. CASE STUDY4-2. When Convergence Unit is Replaced 5-1. Adjusting Procedure in Replacing CRT 5. TROUBLESHOOTING5-2. Adjusting Procedure in Replacing Convergence Unit/Main Def 4 To adjust from outside of digital convergence 6. CONVERGENCE OUTPUT CIRCUIT6-2-1. Signal flow 6-1. Outline6-3. Convergence Block Diagram 7. CONVERGENCE TROUBLESHOOTING CHART VerticalVOLTAGEREG WIDEF BP DV DH