Intel manual Intel 31154 133 MHz PCI Bridge Ball Map-Top View, Left Side

Page 15

Package Information

Figure 3. Intel® 31154 133 MHz PCI Bridge Ball Map—Top View, Left Side

 

 

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A

VSS

P_

P_

P_

P_

VSS

P_

VCCP

P_

VSS

VSS

VCCP

 

ACK64#

AD56

AD60

CBE4#

CBE7#

PAR64

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

B

P_

VSS

P_

P_

P_

P_

P_

P_

P_

P_

P_

P_

 

AD43

AD54

SERR#

AD49

AD50

AD52

AD55

AD57

AD59

AD63

CBE6#

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

C

SCAN_

P_

VSS

P_

VCCP

S_CLK

P_

P_

P_

P_

P_

P_

 

EN

AD48

STOP#

OEN3

AD53

PERR#

AD58

AD61

CBE5#

REQ64#

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

D

S_CLK

P_

QE

VSS

VCCP

P_

VCCP

VSS

VCC

P_

VCC

VSS

 

OEN2

AD47

AD51

AD62

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

E

P_

S_CLK

P_

 

 

 

HS_

HS_

HS_

 

S_TRI

HS_

 

VCCP

R_REF

VSS

LED_

VSS

 

AD38

OEN1

AD45

LSTAT

ENUM#

STATE

FREQ0

 

 

 

 

 

 

 

 

 

OUT

 

 

 

 

 

 

F

VSS

P_

P_

P_

VSS

VCC

VSS

VCC

VSS

VCC

 

 

 

AD42

AD44

AD46

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

G

P_

S_CLK

P_

VCCP

HS_

VSS

 

 

 

 

 

 

 

AD36

OEN0

AD41

SM

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

H

P_

P_

P_

VSS

P_

VCC

 

 

 

 

 

 

 

AD35

AD39

AD40

M66EN

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

J

P_

P_

P_

VCC

SR_

VSS

 

 

 

 

 

 

 

AD33

AD34

AD37

CLK

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

K

VSS

S_

S_

S_

VSS

VCC

 

 

 

VSS

VSS

VSS

 

AD34

AD33

AD32

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

L

P_

S_

S_

VCC

SR_CS

 

 

 

 

VSS

VSS

VSS

 

AD32

AD36

AD35

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

M

VCCP

S_

S_

VSS

SR_DO

 

 

 

 

VSS

VSS

VSS

 

AD39

AD38

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

N

VSS

S_

S_

VCC

SR_DI

 

 

 

 

VSS

VSS

VSS

 

AD41

AD40

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P

VSS

S_

S_

S_

VSS

VSS

 

 

 

VSS

VSS

VSS

 

AD47

AD45

AD43

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R

S_

S_

S_

VCC

S_

VCC

 

 

 

 

 

 

 

AD37

AD49

AD48

GNT7#

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

T

S_VIO

S_

S_

VSS

S_

VSS

 

 

 

 

 

 

 

AD51

AD50

REQ7#

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

U

S_

S_

S_

VCCP

S_

VCC

 

 

 

 

 

 

 

AD42

AD53

AD52

GNT6#

 

 

 

 

 

 

 

V

VSS

S_

S_MAX

S_

VSS

VSS

VCC

VSS

VCC

VSS

 

 

AD55 100

AD54

 

 

 

 

 

 

 

 

 

 

 

W

S_

S_

S_CLK

VCCP

S_

VSS

VSS

VSS

VSS

VSS

VSS

VSS

AD44

REQ2# STABLE

REQ6#

S_

S_

S_

VSS VCCP

S_

VCCP VSS

VCC

S_

VCC

VSS

Y AD46

GNT2#

AD56

AD57

CBE7#

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

AA

NC

S_

VSS

TMODE

S_

S_

S_

S_

S_

S_

S_

S_

REQ1#

2

AD58

AD59

AD61

ACK64#

AD00

PAR64

CBE5#

AD06

AB

S_

VSS

S_

S_

S_

S_

S_

S_

S_

S_

S_

S_

GNT1#

REQ3#

GNT4#

REQ4#

AD60

AD62

AD63

AD01

CBE6#

AD04

CBE0#

 

AC VSS

VCCP

S_

S_

S_

VSS

CRS

S_

S_

VSS

S_

VCCP

 

REQ5#

GNT5#

GNT3#

TEN

CBE4#

AD02

AD03

 

 

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B2240-01

Intel® 31154 133 MHz PCI Bridge Design Guide Design Guide

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Image 15
Contents Design Guide Intel 31154 133 MHz PCI Bridge Design GuideIntel 31154 133 MHz PCI Bridge Design Guide Contents Tables FiguresContents Revision History Date Revision Description001 Initial release Definition About This DocumentTerminology and Definitions Terminology and Definition Sheet 1SHB Terminology and Definition Sheet 2Term ISIIntel 31154 133 MHz PCI Bridge Applications PCI-to-PCI Bridge ConfigurationsIntroduction2 Product OverviewFeatures List Features ListReferences Related External SpecificationsThis page Intentionally Left Blank Package Information Intel 31154 133 MHz PCI Bridge Package Intel 31154 133 MHz PCI Bridge Ball Map-Top View, Left Side Intel 31154 133 MHz PCI Bridge Ball Map-Top View, Right Side Jtag Total Signal CountTotal Signal Count Interface SignalsThis page Intentionally Left Blank Pull-Up/Pull-Down Terminations Sheet 1 Terminations4Pull-Up/Pull-Down Terminations Sheet 2 Secondary PCI SignalsPCI Clocks Pull-Up/Pull-Down Terminations Sheet 3Hot Swap Pull-Up/Pull-Down Terminations Sheet 4Sarblock SarbdisablePull-Up/Pull-Down Terminations Sheet 5 Hardware Straps sampled at the edge of PRST#Serial Eeprom Pull-Up/Pull-Down Terminations Sheet 6Pull-Up/Pull-Down Terminations Sheet 7 VoltagesMiscellaneous SM66EN Pull-Up/Pull-Down Terminations Sheet 8RSTV0 RSRV1/CRSTENNTMASK# Pull-Up/Pull-Down Terminations Sheet 9This page Intentionally Left Blank PCI/PCI-X Voltage Levels PCI/PCI-X InterfacePCI/PCI-X Voltage Levels Interrupt RoutingIdsel Lines Primary Idsel LineSecondary Idsel Lines Secondary Clock Control CompactPCI* Hot Swap Mode SelectOpaque Memory Region Enable Secondary Idsel MaskingPrimary PCI Clocking Mode Secondary PCI Clocking ModePCI-X Initialization Clocking Modes PCI-X Clocking Modes Secondary Bus Frequency InitializationGND MHz Primary-to-Secondary Frequency LimitsPCI-X Initialization Pattern Clock FrequencyRouting Guidelines Crosstalk Effects on Trace Distance and Height CrosstalkEMI Considerations PCB Ground Layout Around ConnectorsIntel 31154 133 MHz PCI Bridge Decoupling Recommendations Power Distribution and DecouplingPins Voltage Capacitor Value Number Decoupling RecommendationsTrace Impedance This page Intentionally Left Blank Add-in Card Routing Parameters PCI-X Layout GuidelinesPCI Clock Layout Guidelines #### PCI-X Slot Guidelines PCI-X Topology Layout GuidelinesMaximum Wiring Lengths for 133 MHz SlotSingle Slot at 133 MHz Lower AD Bus Upper AD Bus SegmentLower AD Bus Upper AD Bus Wiring Lengths for Embedded 133 MHz DesignDual-Slot at 100 MHz Wiring Lengths for 100 MHz Dual-SlotWiring Lengths for Embedded 100 MHz Design W14 Wiring Lengths for 66 MHz Quad-Slot Sheet 1Quad-Slots at 66 MHz W13Wiring Lengths for 66 MHz Quad-Slot Sheet 2 Minimum Length Wiring Lengths for Embedded 66 MHz DesignPCI-X at 33 MHz Embedded PCI-X Specification Picmg 1.2 OverviewAn Example of an ePCI-X System Segment AD Bus Units Wiring Lengths for Picmg 1.2 BackplaneClock Point to Point PCI-X Clock Wiring Lengths for Picmg BackplaneThis page Intentionally Left Blank Analog Power Pins Power ConsiderationsPower Sequencing Eeprom Customer Reference BoardCustomer Reference Board Stackup Probing PCI-X Signals Debug Connectors and Logic Analyzer Connectivity10Logic Analyzer Pod BE2 FrameDevsel TrdyIrdy AD31 PCI-X Signal Name § § This page Intentionally Left Blank Thermal Solutions Operational PowerVoltage Maximum Power Thermal Solutions Design Reference Material References12Related Documents Design Reference MaterialReferences