Intel 31154 manual PCI-X Topology Layout Guidelines, PCI-X Slot Guidelines

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PCI-X Layout Guidelines

7.2PCI-X Topology Layout Guidelines

The PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a, recommends the following guidelines for the number of loads for your PCI-X designs (Table 13). Any deviation from these maximum values requires close attention to layout with regard to loading and trace lengths.

Table 13.

PCI-X Slot Guidelines

 

 

 

 

 

 

Frequency

Maximum Loads

Maximum

 

Number of Slots

 

 

 

 

 

 

 

 

66 MHz

8

4

 

 

 

 

 

100 MHz

4

2

 

 

 

 

 

133 MHz

2

1

 

 

 

 

The following PCI-X design layout considerations are compiled from the white paper Design, Modeling and Simulation Methodology for High Frequency PCI-X Subsystems, available on the http://www.pcisig.com website.

The following results are compiled from the simulation of system models that included system board and add-in cards for different slot configurations and bus speeds (discussed in the white paper mentioned above). This simulation addressed signal-integrity issues including reflective noise, crosstalk noise, overshoot/undershoot voltage, ring-back voltage, settling time, inter-symbol interference, input reference voltage offset, and ground-bounce effects. These results for the slot configurations met the required PCI-X timing characteristics and were within appropriate noise margins.

133 MHz Single-Slot—Included a single connection from the bridge to a single slot.

133 MHz Embedded—Included a single connection from the bridge to one additional device on the system board. Note that this topology was interpolated from the above 133 MHz One- Slot (not based on actual simulation results).

100 MHz Two-Slot Non-Hot-Plug, Balance Star—Included a single connection from the bridge to two slots without hot-plug devices. The connections to the bridge and to each slot came together such that each of the three branches is approximately the same length.

100 MHz Embedded Non-Hot-Plug, Balance Star—Included a single connection from the bridge to three devices. The connections to the bridge and to each device came together such that each of the three branches was approximately the same length. Note that this topology was interpolated from the above 100 MHz Two-Slot (not based on actual simulation results).

66 MHz Four-Slot Non-Hot-Plug—Included a single connection from the bridge to four hot- plug slots.

66 MHz Embedded Non-Hot-Plug—Included a single connection from the bridge to four hot- plug slots. Note that this topology was interpolated from the above 66 MHz Four-Slot (not based on actual simulation results).

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Intel® 31154 133 MHz PCI Bridge Design Guide Design Guide

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Contents Intel 31154 133 MHz PCI Bridge Design Guide Design GuideIntel 31154 133 MHz PCI Bridge Design Guide Contents Figures TablesContents 001 Initial release Revision HistoryDate Revision Description About This Document Terminology and DefinitionsTerminology and Definition Sheet 1 DefinitionTerminology and Definition Sheet 2 TermISI SHBPCI-to-PCI Bridge Configurations Introduction2Product Overview Intel 31154 133 MHz PCI Bridge ApplicationsFeatures List Features ListRelated External Specifications ReferencesThis page Intentionally Left Blank Package Information Intel 31154 133 MHz PCI Bridge Package Intel 31154 133 MHz PCI Bridge Ball Map-Top View, Left Side Intel 31154 133 MHz PCI Bridge Ball Map-Top View, Right Side Total Signal Count Total Signal CountInterface Signals JtagThis page Intentionally Left Blank Terminations4 Pull-Up/Pull-Down Terminations Sheet 1Secondary PCI Signals Pull-Up/Pull-Down Terminations Sheet 2Pull-Up/Pull-Down Terminations Sheet 3 PCI ClocksPull-Up/Pull-Down Terminations Sheet 4 Hot SwapSarbdisable Pull-Up/Pull-Down Terminations Sheet 5Hardware Straps sampled at the edge of PRST# SarblockPull-Up/Pull-Down Terminations Sheet 6 Serial EepromMiscellaneous Pull-Up/Pull-Down Terminations Sheet 7Voltages Pull-Up/Pull-Down Terminations Sheet 8 RSTV0RSRV1/CRSTEN SM66ENPull-Up/Pull-Down Terminations Sheet 9 NTMASK#This page Intentionally Left Blank PCI/PCI-X Interface PCI/PCI-X Voltage LevelsInterrupt Routing PCI/PCI-X Voltage LevelsSecondary Idsel Lines Idsel LinesPrimary Idsel Line CompactPCI* Hot Swap Mode Select Opaque Memory Region EnableSecondary Idsel Masking Secondary Clock ControlPCI-X Initialization Clocking Modes Primary PCI Clocking ModeSecondary PCI Clocking Mode GND PCI-X Clocking ModesSecondary Bus Frequency Initialization Primary-to-Secondary Frequency Limits PCI-X Initialization PatternClock Frequency MHzRouting Guidelines Crosstalk Crosstalk Effects on Trace Distance and HeightPCB Ground Layout Around Connectors EMI ConsiderationsPower Distribution and Decoupling Pins Voltage Capacitor Value NumberDecoupling Recommendations Intel 31154 133 MHz PCI Bridge Decoupling RecommendationsTrace Impedance This page Intentionally Left Blank PCI-X Layout Guidelines Add-in Card Routing ParametersPCI Clock Layout Guidelines #### PCI-X Topology Layout Guidelines PCI-X Slot GuidelinesWiring Lengths for 133 MHz Slot Single Slot at 133 MHzLower AD Bus Upper AD Bus Segment MaximumWiring Lengths for Embedded 133 MHz Design Lower AD Bus Upper AD BusWiring Lengths for 100 MHz Dual-Slot Dual-Slot at 100 MHzWiring Lengths for Embedded 100 MHz Design Wiring Lengths for 66 MHz Quad-Slot Sheet 1 Quad-Slots at 66 MHzW13 W14Wiring Lengths for 66 MHz Quad-Slot Sheet 2 Wiring Lengths for Embedded 66 MHz Design Minimum LengthEmbedded PCI-X Specification Picmg 1.2 Overview PCI-X at 33 MHzAn Example of an ePCI-X System Wiring Lengths for Picmg 1.2 Backplane Segment AD Bus UnitsPCI-X Clock Wiring Lengths for Picmg Backplane Clock Point to PointThis page Intentionally Left Blank Power Considerations Analog Power PinsPower Sequencing Customer Reference Board EepromCustomer Reference Board Stackup Debug Connectors and Logic Analyzer Connectivity10 Probing PCI-X SignalsLogic Analyzer Pod Frame DevselTrdy BE2Irdy AD31 PCI-X Signal Name § § This page Intentionally Left Blank Voltage Maximum Power Thermal SolutionsOperational Power Thermal Solutions References12 Related DocumentsDesign Reference Material Design Reference MaterialReferences