Intel 31154 manual Terminations4, Pull-Up/Pull-Down Terminations Sheet 1

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Terminations

Terminations4

This chapter details all the recommended Intel® 31154 133 MHz PCI Bridge terminations required for the different operating modes.

The chapter provides the recommended pull-up and pull-down terminations for a 31154 layout. Table 5 lists these 31154 termination values. Note that for motherboards, the PCI Local Bus Specification, Revision 2.3 requires that the PCI signals provide the termination resistors.

Table 5.

Pull-Up/Pull-Down Terminations (Sheet 1 of 9)

 

 

 

 

 

 

Signal

 

Pull-Up/Pull-Down or Termination (See Note 1)

 

Comments

 

 

 

 

 

PCI Reset

 

 

 

 

 

 

 

 

 

P_RST#

 

Connect to bus RST# signal on primary PCI bus.

 

 

 

 

 

 

 

S_RST#

 

Connect to bus RST# signal on secondary PCI

 

 

 

bus.

 

 

 

 

 

 

 

 

 

 

Primary PCI Signals

 

 

 

 

 

 

P_AD[31:0]

 

Connect to primary PCI bus AD[31:0].

 

 

 

 

 

 

 

 

 

For 64-bit primary PCI bus:

 

 

 

 

• Connect to the AD[63:32] bits of the primary

 

 

P_AD[63:32]

 

PCI bus.

 

 

 

For 32 bit Primary PCI Bus:

 

 

 

 

 

 

 

 

• Pull up through individual external resistors

 

 

 

 

(see Note 2 and Note 3).

 

 

 

 

 

 

 

P_CBE[3:0]

 

Connect to the CBE[3:0}# bits of the primary PCI

 

 

 

bus.

 

 

 

 

 

 

 

 

 

 

 

 

 

For 64-bit primary PCI bus:

 

 

 

 

• Connect to the CBE[7:4]# bits of the primary

 

 

P_CBE[7:4]#

 

PCI bus.

 

 

 

For 32-bit primary PCI Bus:

 

 

 

 

 

 

 

 

• Pull up through individual external resistors

 

 

 

 

(see Note 2 and Note 3).

 

 

 

 

 

 

 

P_FRAME#

 

Connect to FRAME# of the primary PCI bus.

 

 

 

 

 

 

 

P_DEVSEL#

 

Connect to DEVSEL# of the primary PCI bus.

 

 

 

 

 

 

 

P_IRDY#

 

Connect to IRDY# of the primary PCI bus.

 

 

 

 

 

 

 

P_TRDY#

 

Connect to TRDY# of the primary PCI bus.

 

 

 

 

 

 

 

P_STOP#

 

Connect to STOP# of the primary PCI bus.

 

 

 

 

 

 

 

NOTES:

1.The recommended value for pull-up resistors for PCI applications is 5.6 K(note that the minimum value for PCI 3.3 V signaling RMIN = 2.42 K, RTYP = 8.2 K, as per the PCI Local Bus Specification, Revision 2.3, section 4.3.3).

2.The recommended value for pull-up resistors for PCI-X applications is 8.2 K. For PCI-X, the minimum pull-up resistor value is 5 K, as per the PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0b, section 9.7.

3.For plug-in card implementations, the pull-up must be on the motherboard.

4.Connect PVIO and SVIO pull-up resistors to 5 V or 3.3 V power supply through an external resistor—25 (5 V) or

0 (3.3 V), depending on the signaling level of the primary/secondary PCI bus. Refer to the power-sequencing guidelines in Section 8.2 on page 58.

Intel® 31154 133 MHz PCI Bridge Design Guide Design Guide

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Contents Design Guide Intel 31154 133 MHz PCI Bridge Design GuideIntel 31154 133 MHz PCI Bridge Design Guide Contents Tables FiguresContents Date Revision Description Revision History001 Initial release Definition About This DocumentTerminology and Definitions Terminology and Definition Sheet 1SHB Terminology and Definition Sheet 2Term ISIIntel 31154 133 MHz PCI Bridge Applications PCI-to-PCI Bridge ConfigurationsIntroduction2 Product OverviewFeatures List Features ListReferences Related External SpecificationsThis page Intentionally Left Blank Package Information Intel 31154 133 MHz PCI Bridge Package Intel 31154 133 MHz PCI Bridge Ball Map-Top View, Left Side Intel 31154 133 MHz PCI Bridge Ball Map-Top View, Right Side Jtag Total Signal CountTotal Signal Count Interface SignalsThis page Intentionally Left Blank Pull-Up/Pull-Down Terminations Sheet 1 Terminations4Pull-Up/Pull-Down Terminations Sheet 2 Secondary PCI SignalsPCI Clocks Pull-Up/Pull-Down Terminations Sheet 3Hot Swap Pull-Up/Pull-Down Terminations Sheet 4Sarblock SarbdisablePull-Up/Pull-Down Terminations Sheet 5 Hardware Straps sampled at the edge of PRST#Serial Eeprom Pull-Up/Pull-Down Terminations Sheet 6Voltages Pull-Up/Pull-Down Terminations Sheet 7Miscellaneous SM66EN Pull-Up/Pull-Down Terminations Sheet 8RSTV0 RSRV1/CRSTENNTMASK# Pull-Up/Pull-Down Terminations Sheet 9This page Intentionally Left Blank PCI/PCI-X Voltage Levels PCI/PCI-X InterfacePCI/PCI-X Voltage Levels Interrupt RoutingPrimary Idsel Line Idsel LinesSecondary Idsel Lines Secondary Clock Control CompactPCI* Hot Swap Mode SelectOpaque Memory Region Enable Secondary Idsel MaskingSecondary PCI Clocking Mode Primary PCI Clocking ModePCI-X Initialization Clocking Modes Secondary Bus Frequency Initialization PCI-X Clocking ModesGND MHz Primary-to-Secondary Frequency LimitsPCI-X Initialization Pattern Clock FrequencyRouting Guidelines Crosstalk Effects on Trace Distance and Height CrosstalkEMI Considerations PCB Ground Layout Around ConnectorsIntel 31154 133 MHz PCI Bridge Decoupling Recommendations Power Distribution and DecouplingPins Voltage Capacitor Value Number Decoupling RecommendationsTrace Impedance This page Intentionally Left Blank Add-in Card Routing Parameters PCI-X Layout GuidelinesPCI Clock Layout Guidelines #### PCI-X Slot Guidelines PCI-X Topology Layout GuidelinesMaximum Wiring Lengths for 133 MHz SlotSingle Slot at 133 MHz Lower AD Bus Upper AD Bus SegmentLower AD Bus Upper AD Bus Wiring Lengths for Embedded 133 MHz DesignDual-Slot at 100 MHz Wiring Lengths for 100 MHz Dual-SlotWiring Lengths for Embedded 100 MHz Design W14 Wiring Lengths for 66 MHz Quad-Slot Sheet 1Quad-Slots at 66 MHz W13Wiring Lengths for 66 MHz Quad-Slot Sheet 2 Minimum Length Wiring Lengths for Embedded 66 MHz DesignPCI-X at 33 MHz Embedded PCI-X Specification Picmg 1.2 OverviewAn Example of an ePCI-X System Segment AD Bus Units Wiring Lengths for Picmg 1.2 BackplaneClock Point to Point PCI-X Clock Wiring Lengths for Picmg BackplaneThis page Intentionally Left Blank Analog Power Pins Power ConsiderationsPower Sequencing Eeprom Customer Reference BoardCustomer Reference Board Stackup Probing PCI-X Signals Debug Connectors and Logic Analyzer Connectivity10Logic Analyzer Pod BE2 FrameDevsel TrdyIrdy AD31 PCI-X Signal Name § § This page Intentionally Left Blank Operational Power Thermal SolutionsVoltage Maximum Power Thermal Solutions Design Reference Material References12Related Documents Design Reference MaterialReferences