Terminations
Terminations4
This chapter details all the recommended Intel® 31154 133 MHz PCI Bridge terminations required for the different operating modes.
The chapter provides the recommended
Table 5. |
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Signal |
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PCI Reset |
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P_RST# |
| Connect to bus RST# signal on primary PCI bus. |
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S_RST# |
| Connect to bus RST# signal on secondary PCI |
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| bus. |
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Primary PCI Signals |
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P_AD[31:0] |
| Connect to primary PCI bus AD[31:0]. |
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| For |
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| • Connect to the AD[63:32] bits of the primary |
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P_AD[63:32] |
| PCI bus. |
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| For 32 bit Primary PCI Bus: |
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| • Pull up through individual external resistors |
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| (see Note 2 and Note 3). |
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P_CBE[3:0] |
| Connect to the CBE[3:0}# bits of the primary PCI |
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| bus. |
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| For |
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| • Connect to the CBE[7:4]# bits of the primary |
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P_CBE[7:4]# |
| PCI bus. |
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| For |
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| • Pull up through individual external resistors |
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| (see Note 2 and Note 3). |
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P_FRAME# |
| Connect to FRAME# of the primary PCI bus. |
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P_DEVSEL# |
| Connect to DEVSEL# of the primary PCI bus. |
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P_IRDY# |
| Connect to IRDY# of the primary PCI bus. |
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P_TRDY# |
| Connect to TRDY# of the primary PCI bus. |
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P_STOP# |
| Connect to STOP# of the primary PCI bus. |
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NOTES:
1.The recommended value for
2.The recommended value for
3.For
4.Connect PVIO and SVIO
0 Ω (3.3 V), depending on the signaling level of the primary/secondary PCI bus. Refer to the
Intel® 31154 133 MHz PCI Bridge Design Guide Design Guide | 19 |