Intel 31154 manual Wiring Lengths for Embedded 133 MHz Design, Lower AD Bus Upper AD Bus

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PCI-X Layout Guidelines

7.2.1.1Intel® 31154 133 MHz PCI Bridge Embedded Application at 133 MHz

Figure 10 shows the 31154 application in a stand-alone embedded application. In this application the 31154 is shown driving a single PCI device. Table 15 shows the corresponding wiring lengths to use as a reference.

Figure 10. Embedded Intel® 31154 133 MHz PCI Bridge Design 133 MHz PCI-X Layout

 

W1

W2

 

 

PCI

 

 

Agent

I/O Buffer

IDSEL

 

 

 

 

W3

W4

 

 

B3058-01

Table 15.

Wiring Lengths for Embedded 133 MHz Design

 

 

 

 

 

 

 

 

 

 

 

Lower AD Bus

Upper AD Bus

 

 

Segment

 

 

 

 

Units

 

Minimum

Maximum

Minimum

Maximum

 

 

 

 

 

Length

Length

Length

Length

 

 

 

 

 

 

 

 

 

W1

5.5

10.5

4.5

9.5

inches

 

 

 

 

 

 

 

 

W2

0.75

1.5

1.75

2.75

inches

 

 

 

 

 

 

 

 

W3

0.1

0.1

inches

 

 

 

 

 

 

 

 

W4

1.725

1.725

inches

 

 

 

 

 

 

 

46

Intel® 31154 133 MHz PCI Bridge Design Guide Design Guide

Image 46
Contents Intel 31154 133 MHz PCI Bridge Design Guide Design GuideIntel 31154 133 MHz PCI Bridge Design Guide Contents Figures TablesContents Date Revision Description Revision History001 Initial release Terminology and Definition Sheet 1 About This DocumentTerminology and Definitions DefinitionISI Terminology and Definition Sheet 2Term SHBProduct Overview PCI-to-PCI Bridge ConfigurationsIntroduction2 Intel 31154 133 MHz PCI Bridge ApplicationsFeatures List Features ListRelated External Specifications ReferencesThis page Intentionally Left Blank Package Information Intel 31154 133 MHz PCI Bridge Package Intel 31154 133 MHz PCI Bridge Ball Map-Top View, Left Side Intel 31154 133 MHz PCI Bridge Ball Map-Top View, Right Side Interface Signals Total Signal CountTotal Signal Count JtagThis page Intentionally Left Blank Terminations4 Pull-Up/Pull-Down Terminations Sheet 1Secondary PCI Signals Pull-Up/Pull-Down Terminations Sheet 2Pull-Up/Pull-Down Terminations Sheet 3 PCI ClocksPull-Up/Pull-Down Terminations Sheet 4 Hot SwapHardware Straps sampled at the edge of PRST# SarbdisablePull-Up/Pull-Down Terminations Sheet 5 SarblockPull-Up/Pull-Down Terminations Sheet 6 Serial EepromVoltages Pull-Up/Pull-Down Terminations Sheet 7Miscellaneous RSRV1/CRSTEN Pull-Up/Pull-Down Terminations Sheet 8RSTV0 SM66ENPull-Up/Pull-Down Terminations Sheet 9 NTMASK#This page Intentionally Left Blank Interrupt Routing PCI/PCI-X InterfacePCI/PCI-X Voltage Levels PCI/PCI-X Voltage LevelsPrimary Idsel Line Idsel LinesSecondary Idsel Lines Secondary Idsel Masking CompactPCI* Hot Swap Mode SelectOpaque Memory Region Enable Secondary Clock ControlSecondary PCI Clocking Mode Primary PCI Clocking ModePCI-X Initialization Clocking Modes Secondary Bus Frequency Initialization PCI-X Clocking ModesGND Clock Frequency Primary-to-Secondary Frequency LimitsPCI-X Initialization Pattern MHzRouting Guidelines Crosstalk Crosstalk Effects on Trace Distance and HeightPCB Ground Layout Around Connectors EMI ConsiderationsDecoupling Recommendations Power Distribution and DecouplingPins Voltage Capacitor Value Number Intel 31154 133 MHz PCI Bridge Decoupling RecommendationsTrace Impedance This page Intentionally Left Blank PCI-X Layout Guidelines Add-in Card Routing ParametersPCI Clock Layout Guidelines #### PCI-X Topology Layout Guidelines PCI-X Slot GuidelinesLower AD Bus Upper AD Bus Segment Wiring Lengths for 133 MHz SlotSingle Slot at 133 MHz MaximumWiring Lengths for Embedded 133 MHz Design Lower AD Bus Upper AD BusWiring Lengths for 100 MHz Dual-Slot Dual-Slot at 100 MHzWiring Lengths for Embedded 100 MHz Design W13 Wiring Lengths for 66 MHz Quad-Slot Sheet 1Quad-Slots at 66 MHz W14Wiring Lengths for 66 MHz Quad-Slot Sheet 2 Wiring Lengths for Embedded 66 MHz Design Minimum LengthEmbedded PCI-X Specification Picmg 1.2 Overview PCI-X at 33 MHzAn Example of an ePCI-X System Wiring Lengths for Picmg 1.2 Backplane Segment AD Bus UnitsPCI-X Clock Wiring Lengths for Picmg Backplane Clock Point to PointThis page Intentionally Left Blank Power Considerations Analog Power PinsPower Sequencing Customer Reference Board EepromCustomer Reference Board Stackup Debug Connectors and Logic Analyzer Connectivity10 Probing PCI-X SignalsLogic Analyzer Pod Trdy FrameDevsel BE2Irdy AD31 PCI-X Signal Name § § This page Intentionally Left Blank Operational Power Thermal SolutionsVoltage Maximum Power Thermal Solutions Design Reference Material References12Related Documents Design Reference MaterialReferences