Intel 31154 About This Document, Terminology and Definitions, Terminology and Definition Sheet 1

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About This Document

About This Document

1

 

 

This document provides layout information and guidelines for designing platform or add-in board applications with the Intel® 31154 133 MHz PCI Bridge.

This document is intended to be used as a guideline only. Intel recommends that you employ best- known design practices with board-level simulation, signal-integrity testing, and validation for a robust design. Please note that this design guide focuses on specific design considerations for the 31154 Bridge and is not intended to be an all-inclusive list of all good design practices. Use this guide as a starting point, and use empirical data to optimize your particular design.

1.1Terminology and Definitions

Table 1.

Terminology and Definition (Sheet 1 of 2)

 

 

 

 

 

 

 

 

 

 

 

 

Term

 

 

 

 

 

 

Definition

 

 

 

 

 

 

 

 

 

 

 

31154

Intel® 31154 133 MHz PCI Bridge

 

 

 

 

 

 

 

 

 

 

Stripline in a PCB is composed of the

 

 

 

 

 

 

 

 

 

conductor inserted in a dielectric with GND

 

 

 

 

 

 

 

 

 

planes to the top and bottom, as shown in the

 

Stripline

 

 

 

 

 

 

 

cross-section diagram at left.

 

 

 

 

 

 

 

 

NOTE: An easy way to distinguish stripline

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

from microstrip is that you need to

 

 

 

 

 

 

 

 

 

strip away layers of the board to view

 

 

 

 

 

 

 

 

 

the trace on stripline.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Microstrip in a PCB is composed of the

 

 

 

 

 

 

 

 

 

 

Microstrip

 

 

 

 

 

 

 

conductor on the top layer above the

 

 

 

 

 

 

 

 

dielectric with a ground plane below, as

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

shown in the cross-section diagram at left.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Prepreg is material used for the lamination process of manufacturing PCBs. It consists of a

 

Prepreg

layer of epoxy material that is placed between two cores. This layer melts into epoxy when

 

 

heated and forms around adjacent traces.

 

 

 

 

 

 

 

 

 

 

 

Core

Core material is used for the lamination process of manufacturing PCBs. This material is two-

 

sided laminate with copper on each side. The core is an internal layer that is etched.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Layer 1: copper

Printed circuit board: An example PCB

 

 

 

 

 

 

 

manufacturing process consists of the

 

 

 

 

 

 

 

Prepreg

following steps:

 

 

 

 

 

 

 

Layer 2: GND

• A PCB consists of alternating layers of

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Core

core and prepreg stacked.

 

 

 

 

 

 

 

• The finished PCB is heated and cured.

 

PCB

 

 

 

 

 

Layer 3: VCC

 

 

 

 

 

 

• The via holes are drilled.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Prepreg

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Layer 4: copper

• Plating covers holes and outer surfaces.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

• Etching removes unwanted copper.

 

 

Example of a cross-section of

• The PCB is tinned, coated with solder

 

 

 

a four-layer stack

 

 

 

mask, and silk-screened.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Intel® 31154 133 MHz PCI Bridge Design Guide Design Guide

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Contents Design Guide Intel 31154 133 MHz PCI Bridge Design GuideIntel 31154 133 MHz PCI Bridge Design Guide Contents Tables FiguresContents Date Revision Description Revision History001 Initial release Definition About This DocumentTerminology and Definitions Terminology and Definition Sheet 1SHB Terminology and Definition Sheet 2Term ISIIntel 31154 133 MHz PCI Bridge Applications PCI-to-PCI Bridge ConfigurationsIntroduction2 Product OverviewFeatures List Features ListReferences Related External SpecificationsThis page Intentionally Left Blank Package Information Intel 31154 133 MHz PCI Bridge Package Intel 31154 133 MHz PCI Bridge Ball Map-Top View, Left Side Intel 31154 133 MHz PCI Bridge Ball Map-Top View, Right Side Jtag Total Signal CountTotal Signal Count Interface SignalsThis page Intentionally Left Blank Pull-Up/Pull-Down Terminations Sheet 1 Terminations4Pull-Up/Pull-Down Terminations Sheet 2 Secondary PCI SignalsPCI Clocks Pull-Up/Pull-Down Terminations Sheet 3Hot Swap Pull-Up/Pull-Down Terminations Sheet 4Sarblock SarbdisablePull-Up/Pull-Down Terminations Sheet 5 Hardware Straps sampled at the edge of PRST#Serial Eeprom Pull-Up/Pull-Down Terminations Sheet 6Voltages Pull-Up/Pull-Down Terminations Sheet 7Miscellaneous SM66EN Pull-Up/Pull-Down Terminations Sheet 8RSTV0 RSRV1/CRSTENNTMASK# Pull-Up/Pull-Down Terminations Sheet 9This page Intentionally Left Blank PCI/PCI-X Voltage Levels PCI/PCI-X InterfacePCI/PCI-X Voltage Levels Interrupt RoutingPrimary Idsel Line Idsel LinesSecondary Idsel Lines Secondary Clock Control CompactPCI* Hot Swap Mode SelectOpaque Memory Region Enable Secondary Idsel MaskingSecondary PCI Clocking Mode Primary PCI Clocking ModePCI-X Initialization Clocking Modes Secondary Bus Frequency Initialization PCI-X Clocking ModesGND MHz Primary-to-Secondary Frequency LimitsPCI-X Initialization Pattern Clock FrequencyRouting Guidelines Crosstalk Effects on Trace Distance and Height CrosstalkEMI Considerations PCB Ground Layout Around ConnectorsIntel 31154 133 MHz PCI Bridge Decoupling Recommendations Power Distribution and DecouplingPins Voltage Capacitor Value Number Decoupling RecommendationsTrace Impedance This page Intentionally Left Blank Add-in Card Routing Parameters PCI-X Layout GuidelinesPCI Clock Layout Guidelines #### PCI-X Slot Guidelines PCI-X Topology Layout GuidelinesMaximum Wiring Lengths for 133 MHz SlotSingle Slot at 133 MHz Lower AD Bus Upper AD Bus SegmentLower AD Bus Upper AD Bus Wiring Lengths for Embedded 133 MHz DesignDual-Slot at 100 MHz Wiring Lengths for 100 MHz Dual-SlotWiring Lengths for Embedded 100 MHz Design W14 Wiring Lengths for 66 MHz Quad-Slot Sheet 1Quad-Slots at 66 MHz W13Wiring Lengths for 66 MHz Quad-Slot Sheet 2 Minimum Length Wiring Lengths for Embedded 66 MHz DesignPCI-X at 33 MHz Embedded PCI-X Specification Picmg 1.2 OverviewAn Example of an ePCI-X System Segment AD Bus Units Wiring Lengths for Picmg 1.2 BackplaneClock Point to Point PCI-X Clock Wiring Lengths for Picmg BackplaneThis page Intentionally Left Blank Analog Power Pins Power ConsiderationsPower Sequencing Eeprom Customer Reference BoardCustomer Reference Board Stackup Probing PCI-X Signals Debug Connectors and Logic Analyzer Connectivity10Logic Analyzer Pod BE2 FrameDevsel TrdyIrdy AD31 PCI-X Signal Name § § This page Intentionally Left Blank Operational Power Thermal SolutionsVoltage Maximum Power Thermal Solutions Design Reference Material References12Related Documents Design Reference MaterialReferences