Intel 31154 manual Primary Idsel Line, Secondary Idsel Lines

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PCI/PCI-X Interface

5.3IDSEL Lines

The IDSEL lines act as chip selects during the configuration cycles. Configuration cycles allow read and write access to one of the device configuration space registers. As in PCI, the IDSEL lines can be mapped to upper address lines, which are unused during the configuration cycles.

5.3.1Primary IDSEL Line

Figure 5 provides an example of the 31154 used as an embedded controller connected to four PCI devices. Note that AD16 is typically reserved for a PCI/PCI-X bridge.

When the 31154 is used as the primary interface to a plug-in card, the primary IDSEL line must be routed from the PCI connector to the P_IDSEL pin.

When the 31154 is used in an embedded application, PCI AD16 is used for source bridges. This line (AD16) must be connected to the P_IDSEL line through a 2 Kresistor.

Figure 5.

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5.3.2Secondary IDSEL Lines

The PCI specification recommends a specific resistor value of 2 K±5%. A smaller value may be used as long as system analysis ensures that timing and noise budgets for the AD bit are met.

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Intel® 31154 133 MHz PCI Bridge Design Guide Design Guide

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Contents Intel 31154 133 MHz PCI Bridge Design Guide Design GuideIntel 31154 133 MHz PCI Bridge Design Guide Contents Figures TablesContents Revision History Date Revision Description001 Initial release Terminology and Definition Sheet 1 About This DocumentTerminology and Definitions DefinitionISI Terminology and Definition Sheet 2Term SHBProduct Overview PCI-to-PCI Bridge ConfigurationsIntroduction2 Intel 31154 133 MHz PCI Bridge ApplicationsFeatures List Features ListRelated External Specifications ReferencesThis page Intentionally Left Blank Package Information Intel 31154 133 MHz PCI Bridge Package Intel 31154 133 MHz PCI Bridge Ball Map-Top View, Left Side Intel 31154 133 MHz PCI Bridge Ball Map-Top View, Right Side Interface Signals Total Signal CountTotal Signal Count JtagThis page Intentionally Left Blank Terminations4 Pull-Up/Pull-Down Terminations Sheet 1Secondary PCI Signals Pull-Up/Pull-Down Terminations Sheet 2Pull-Up/Pull-Down Terminations Sheet 3 PCI ClocksPull-Up/Pull-Down Terminations Sheet 4 Hot SwapHardware Straps sampled at the edge of PRST# SarbdisablePull-Up/Pull-Down Terminations Sheet 5 SarblockPull-Up/Pull-Down Terminations Sheet 6 Serial EepromPull-Up/Pull-Down Terminations Sheet 7 VoltagesMiscellaneous RSRV1/CRSTEN Pull-Up/Pull-Down Terminations Sheet 8RSTV0 SM66ENPull-Up/Pull-Down Terminations Sheet 9 NTMASK#This page Intentionally Left Blank Interrupt Routing PCI/PCI-X InterfacePCI/PCI-X Voltage Levels PCI/PCI-X Voltage LevelsIdsel Lines Primary Idsel LineSecondary Idsel Lines Secondary Idsel Masking CompactPCI* Hot Swap Mode SelectOpaque Memory Region Enable Secondary Clock ControlPrimary PCI Clocking Mode Secondary PCI Clocking ModePCI-X Initialization Clocking Modes PCI-X Clocking Modes Secondary Bus Frequency InitializationGND Clock Frequency Primary-to-Secondary Frequency LimitsPCI-X Initialization Pattern MHzRouting Guidelines Crosstalk Crosstalk Effects on Trace Distance and HeightPCB Ground Layout Around Connectors EMI ConsiderationsDecoupling Recommendations Power Distribution and DecouplingPins Voltage Capacitor Value Number Intel 31154 133 MHz PCI Bridge Decoupling RecommendationsTrace Impedance This page Intentionally Left Blank PCI-X Layout Guidelines Add-in Card Routing ParametersPCI Clock Layout Guidelines #### PCI-X Topology Layout Guidelines PCI-X Slot GuidelinesLower AD Bus Upper AD Bus Segment Wiring Lengths for 133 MHz SlotSingle Slot at 133 MHz MaximumWiring Lengths for Embedded 133 MHz Design Lower AD Bus Upper AD BusWiring Lengths for 100 MHz Dual-Slot Dual-Slot at 100 MHzWiring Lengths for Embedded 100 MHz Design W13 Wiring Lengths for 66 MHz Quad-Slot Sheet 1Quad-Slots at 66 MHz W14Wiring Lengths for 66 MHz Quad-Slot Sheet 2 Wiring Lengths for Embedded 66 MHz Design Minimum LengthEmbedded PCI-X Specification Picmg 1.2 Overview PCI-X at 33 MHzAn Example of an ePCI-X System Wiring Lengths for Picmg 1.2 Backplane Segment AD Bus UnitsPCI-X Clock Wiring Lengths for Picmg Backplane Clock Point to PointThis page Intentionally Left Blank Power Considerations Analog Power PinsPower Sequencing Customer Reference Board EepromCustomer Reference Board Stackup Debug Connectors and Logic Analyzer Connectivity10 Probing PCI-X SignalsLogic Analyzer Pod Trdy FrameDevsel BE2Irdy AD31 PCI-X Signal Name § § This page Intentionally Left Blank Thermal Solutions Operational PowerVoltage Maximum Power Thermal Solutions Design Reference Material References12Related Documents Design Reference MaterialReferences