Intel 31154 manual Power Distribution and Decoupling, Decoupling Recommendations, Capacitors

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Routing Guidelines

6.3Power Distribution and Decoupling

Ensure that there is ample decoupling to ground for the power planes, to minimize the effects of the switching currents.

Inadequate high-frequency decoupling results in intermittent and unreliable behavior.

As a general guideline, it is recommended that you use the largest easily available capacitor in the lowest-inductance package. The high-speed decoupling capacitor must be placed as close to the pin as possible, with a short, wide trace.

Three types of decoupling are described below:

•Bulk capacitor: Bulk capacitors consist of electrolytic or tantalum capacitors. These capacitors supply large reservoirs of charge, but they are useful only at lower frequencies due to lead-inductance effects. Bulk capacitors can be located anywhere on the board.

•High-frequency ceramic capacitor: For fast switching currents, high-frequency low- inductance capacitors are most effective. Place these capacitors as close to the device being decoupled as possible. This placement minimizes the parasitic resistance and inductance associated with board traces and vias.

•Inter-plane capacitor: Use an inter-plane capacitor between power and ground planes to reduce the effective plane impedance at high frequencies. The general guideline for placing capacitors is to place high-frequency ceramic capacitors as close as possible to the module.

6.3.1Decoupling Recommendations

This section describes the recommended high-frequency and bulk decoupling for each of the 31154 power supplies based on our simulations. The recommendations are listed in Table 11.

Table 11. Intel® 31154 133 MHz PCI Bridge Decoupling Recommendations

Pins

Voltage

Capacitor Value

Capacitor

Number of

Notes

(∝F)

Package

Capacitors

 

 

 

 

 

 

 

 

 

VCC33

3.3 V

22

1210

3

2, 3, 4

 

 

 

 

 

 

VCC33

3.3 V

0.1

603

12

2, 3, 4

 

 

 

 

 

 

VCC33

3.3 V

150

7343

1

2, 3, 4

 

 

 

 

 

 

VCC

1.3 V

22

1210

3

2, 3, 4

 

 

 

 

 

 

VCC

1.3 V

0.1

603

12

2, 3, 4

 

 

 

 

 

 

P_VIO, S_VIO

3.3 V/5.0 V

22

1210

1

2, 3, 4

 

 

 

 

 

 

P_VIO, S_VIO

3.3 V/5.0 V

0.1

603

4

2, 3, 4

 

 

 

 

 

 

P_VCCA,

 

Refer to

 

 

 

1.3 V

Section 8.1 on

–

–

1, 2, 3, 4

S_VCCA

 

page 57.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NOTES:

 

 

 

 

 

1.Separate capacitor required only when P_VIO and S_VIO are not connected to VCC33.

2.Polymerized organic capacitors are recommended for bulk.

3.X5R, X7R, or COG are recommended for ceramics.

4.Place all capacitors as close as possible to associated pins to minimize inductance.

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Intel® 31154 133 MHz PCI Bridge Design Guide Design Guide

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Contents Intel 31154 133 MHz PCI Bridge Design Guide Design GuideIntel 31154 133 MHz PCI Bridge Design Guide Contents Figures TablesContents 001 Initial release Revision HistoryDate Revision Description Terminology and Definition Sheet 1 About This DocumentTerminology and Definitions DefinitionISI Terminology and Definition Sheet 2Term SHBProduct Overview PCI-to-PCI Bridge ConfigurationsIntroduction2 Intel 31154 133 MHz PCI Bridge ApplicationsFeatures List Features ListRelated External Specifications ReferencesThis page Intentionally Left Blank Package Information Intel 31154 133 MHz PCI Bridge Package Intel 31154 133 MHz PCI Bridge Ball Map-Top View, Left Side Intel 31154 133 MHz PCI Bridge Ball Map-Top View, Right Side Interface Signals Total Signal CountTotal Signal Count JtagThis page Intentionally Left Blank Terminations4 Pull-Up/Pull-Down Terminations Sheet 1Secondary PCI Signals Pull-Up/Pull-Down Terminations Sheet 2Pull-Up/Pull-Down Terminations Sheet 3 PCI ClocksPull-Up/Pull-Down Terminations Sheet 4 Hot SwapHardware Straps sampled at the edge of PRST# SarbdisablePull-Up/Pull-Down Terminations Sheet 5 SarblockPull-Up/Pull-Down Terminations Sheet 6 Serial EepromMiscellaneous Pull-Up/Pull-Down Terminations Sheet 7Voltages RSRV1/CRSTEN Pull-Up/Pull-Down Terminations Sheet 8RSTV0 SM66ENPull-Up/Pull-Down Terminations Sheet 9 NTMASK#This page Intentionally Left Blank Interrupt Routing PCI/PCI-X InterfacePCI/PCI-X Voltage Levels PCI/PCI-X Voltage LevelsSecondary Idsel Lines Idsel LinesPrimary Idsel Line Secondary Idsel Masking CompactPCI* Hot Swap Mode SelectOpaque Memory Region Enable Secondary Clock ControlPCI-X Initialization Clocking Modes Primary PCI Clocking ModeSecondary PCI Clocking Mode GND PCI-X Clocking ModesSecondary Bus Frequency Initialization Clock Frequency Primary-to-Secondary Frequency LimitsPCI-X Initialization Pattern MHzRouting Guidelines Crosstalk Crosstalk Effects on Trace Distance and HeightPCB Ground Layout Around Connectors EMI ConsiderationsDecoupling Recommendations Power Distribution and DecouplingPins Voltage Capacitor Value Number Intel 31154 133 MHz PCI Bridge Decoupling RecommendationsTrace Impedance This page Intentionally Left Blank PCI-X Layout Guidelines Add-in Card Routing ParametersPCI Clock Layout Guidelines #### PCI-X Topology Layout Guidelines PCI-X Slot GuidelinesLower AD Bus Upper AD Bus Segment Wiring Lengths for 133 MHz SlotSingle Slot at 133 MHz MaximumWiring Lengths for Embedded 133 MHz Design Lower AD Bus Upper AD BusWiring Lengths for 100 MHz Dual-Slot Dual-Slot at 100 MHzWiring Lengths for Embedded 100 MHz Design W13 Wiring Lengths for 66 MHz Quad-Slot Sheet 1Quad-Slots at 66 MHz W14Wiring Lengths for 66 MHz Quad-Slot Sheet 2 Wiring Lengths for Embedded 66 MHz Design Minimum LengthEmbedded PCI-X Specification Picmg 1.2 Overview PCI-X at 33 MHzAn Example of an ePCI-X System Wiring Lengths for Picmg 1.2 Backplane Segment AD Bus UnitsPCI-X Clock Wiring Lengths for Picmg Backplane Clock Point to PointThis page Intentionally Left Blank Power Considerations Analog Power PinsPower Sequencing Customer Reference Board EepromCustomer Reference Board Stackup Debug Connectors and Logic Analyzer Connectivity10 Probing PCI-X SignalsLogic Analyzer Pod Trdy FrameDevsel BE2Irdy AD31 PCI-X Signal Name § § This page Intentionally Left Blank Voltage Maximum Power Thermal SolutionsOperational Power Thermal Solutions Design Reference Material References12Related Documents Design Reference MaterialReferences
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