7.2.3Quad-Slots at 66 MHz
Figure 13 shows one of the bridge secondary AD lines branching to four segments with each segment connecting to a slot connector to a buffer on an add-in card. The first segment representing an upper address line branches to a series resistor to become the IDSEL line for slot 1. Table 18 shows the corresponding wiring lengths to use as a reference.
Figure 13. Quad-Slots 66 MHz Topology
| W1 |
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| W13 |
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| PCI |
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| Connector | PCI Agent 1 |
I/O Buffer | W14 | W15 | W16 | |
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| Slot 1 |
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| W22 |
| PCI | W23 |
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| Connector | PCI Agent 2 |
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| Slot 2 |
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| W32 |
| PCI | W33 |
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| Connector | PCI Agent 3 |
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| Slot 3 |
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| W42 |
| PCI | W43 |
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| Connector | PCI Agent 4 |
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| Slot 4 |
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Table 18. Wiring Lengths for 66 MHz Quad-Slot (Sheet 1 of 2)
| Lower AD Bus | Upper AD Bus |
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Segment |
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| Units | |
Minimum | Maximum | Minimum | Maximum | |||
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| Length | Length | Length | Length |
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W1 | 5 | 7 | 2.5 | 7 | inches | |
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W13 | 0.75 | 1.5 | 1.75 | 2.75 | inches | |
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W14 | 0.1 | 0.1 | – | – | inches | |
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Intel® 31154 133 MHz PCI Bridge Design Guide Design Guide | 49 |