Intel 31154 manual PCI-X Clocking Modes, Secondary Bus Frequency Initialization, Gnd

Page 33

PCI/PCI-X Interface

Table 8.

PCI-X Clocking Modes

 

 

 

 

 

 

 

 

PCI-X Mode

PCI Mode

PCIXCAP (pin on

P_M66EN

 

PCI connector)

 

 

 

 

 

 

 

 

 

 

Not capable

33 MHz

GND

GND

 

 

 

 

 

 

Not capable

66 MHz

GND

Not connected

 

 

 

 

 

 

PCI-X/66 MHz

33 MHz

Pull down

GND

 

 

 

 

 

 

PCI-X/66 MHz

66 MHz

Pull down

Not connected

 

 

 

 

 

 

PCI-X/133 MHz

33 MHz

Not connected

Ground

 

 

 

 

 

 

PCI-X/133 MHz

66 MHz

Not connected

Not connected

 

 

 

 

 

Table 9.

Secondary Bus Frequency Initialization

 

 

 

 

 

 

 

 

 

S_M66EN

 

S_PCIXCAP

S_MAX100

Conventional PCI

PCI-X Frequency

Typical Slot

 

Frequency

Loading1

Ground

 

Ground

33 MHz

Not capable

 

 

 

 

 

 

 

 

Not connected

 

Ground

66 MHz

Not capable

 

 

 

 

 

 

 

 

Ground

 

Pull-down

33 MHz

PCI-X 66 MHz

Typical setting for

 

four slots

 

 

 

 

 

 

 

 

 

 

 

 

 

Not connected

 

Pull-down

66 MHz

PCI-X 66 MHz

 

 

 

 

 

 

 

 

Ground

 

Not connected

1

33 MHz

PCI-X 100 MHz

 

 

 

 

 

 

 

 

Not Connected

 

Not Connected

1

66 MHz

PCI-X 100 MHz

Typical setting for

 

two slots

 

 

 

 

 

 

 

 

 

 

 

 

 

Ground

 

Not Connected

0

33 MHz

PCI-X 133 MHz

 

 

 

 

 

 

 

 

Not Connected

 

Not Connected

0

66 MHz

PCI-X 133 MHz

Typical setting for

 

one slot

 

 

 

 

 

 

 

 

 

 

 

 

 

NOTE:

 

 

 

 

 

 

1. Simulation is suggested for any deviation from typical slot loading recommendations.

 

Intel® 31154 133 MHz PCI Bridge Design Guide Design Guide

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Image 33
Contents Design Guide Intel 31154 133 MHz PCI Bridge Design GuideIntel 31154 133 MHz PCI Bridge Design Guide Contents Tables FiguresContents Revision History Date Revision Description001 Initial release Terminology and Definitions About This DocumentTerminology and Definition Sheet 1 DefinitionTerm Terminology and Definition Sheet 2ISI SHBIntroduction2 PCI-to-PCI Bridge ConfigurationsProduct Overview Intel 31154 133 MHz PCI Bridge ApplicationsFeatures List Features ListReferences Related External SpecificationsThis page Intentionally Left Blank Package Information Intel 31154 133 MHz PCI Bridge Package Intel 31154 133 MHz PCI Bridge Ball Map-Top View, Left Side Intel 31154 133 MHz PCI Bridge Ball Map-Top View, Right Side Total Signal Count Total Signal CountInterface Signals JtagThis page Intentionally Left Blank Pull-Up/Pull-Down Terminations Sheet 1 Terminations4Pull-Up/Pull-Down Terminations Sheet 2 Secondary PCI SignalsPCI Clocks Pull-Up/Pull-Down Terminations Sheet 3Hot Swap Pull-Up/Pull-Down Terminations Sheet 4Pull-Up/Pull-Down Terminations Sheet 5 SarbdisableHardware Straps sampled at the edge of PRST# SarblockSerial Eeprom Pull-Up/Pull-Down Terminations Sheet 6Pull-Up/Pull-Down Terminations Sheet 7 VoltagesMiscellaneous RSTV0 Pull-Up/Pull-Down Terminations Sheet 8RSRV1/CRSTEN SM66ENNTMASK# Pull-Up/Pull-Down Terminations Sheet 9This page Intentionally Left Blank PCI/PCI-X Voltage Levels PCI/PCI-X InterfaceInterrupt Routing PCI/PCI-X Voltage LevelsIdsel Lines Primary Idsel LineSecondary Idsel Lines Opaque Memory Region Enable CompactPCI* Hot Swap Mode SelectSecondary Idsel Masking Secondary Clock ControlPrimary PCI Clocking Mode Secondary PCI Clocking ModePCI-X Initialization Clocking Modes PCI-X Clocking Modes Secondary Bus Frequency InitializationGND PCI-X Initialization Pattern Primary-to-Secondary Frequency LimitsClock Frequency MHzRouting Guidelines Crosstalk Effects on Trace Distance and Height CrosstalkEMI Considerations PCB Ground Layout Around ConnectorsPins Voltage Capacitor Value Number Power Distribution and DecouplingDecoupling Recommendations Intel 31154 133 MHz PCI Bridge Decoupling RecommendationsTrace Impedance This page Intentionally Left Blank Add-in Card Routing Parameters PCI-X Layout GuidelinesPCI Clock Layout Guidelines #### PCI-X Slot Guidelines PCI-X Topology Layout GuidelinesSingle Slot at 133 MHz Wiring Lengths for 133 MHz SlotLower AD Bus Upper AD Bus Segment MaximumLower AD Bus Upper AD Bus Wiring Lengths for Embedded 133 MHz DesignDual-Slot at 100 MHz Wiring Lengths for 100 MHz Dual-SlotWiring Lengths for Embedded 100 MHz Design Quad-Slots at 66 MHz Wiring Lengths for 66 MHz Quad-Slot Sheet 1W13 W14Wiring Lengths for 66 MHz Quad-Slot Sheet 2 Minimum Length Wiring Lengths for Embedded 66 MHz DesignPCI-X at 33 MHz Embedded PCI-X Specification Picmg 1.2 OverviewAn Example of an ePCI-X System Segment AD Bus Units Wiring Lengths for Picmg 1.2 BackplaneClock Point to Point PCI-X Clock Wiring Lengths for Picmg BackplaneThis page Intentionally Left Blank Analog Power Pins Power ConsiderationsPower Sequencing Eeprom Customer Reference BoardCustomer Reference Board Stackup Probing PCI-X Signals Debug Connectors and Logic Analyzer Connectivity10Logic Analyzer Pod Devsel FrameTrdy BE2Irdy AD31 PCI-X Signal Name § § This page Intentionally Left Blank Thermal Solutions Operational PowerVoltage Maximum Power Thermal Solutions Related Documents References12Design Reference Material Design Reference MaterialReferences