Intel 31154 manual Crosstalk Effects on Trace Distance and Height

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Routing Guidelines

6.1Crosstalk

Crosstalk is caused by capacitive and inductive coupling between signals. Crosstalk is composed of both backward and forward crosstalk components. Backward crosstalk creates an induced signal on a victim network that propagates in the opposite direction of the aggressor signal. Forward crosstalk creates a signal that propagates in the same direction as the aggressor signal.

Circuit-board analysis software is used to analyze your board layout for crosstalk problems. Examples of 2D analysis tools include Ansoft* Parasitic Parameters* and Quad Design* XFS*. Crosstalk problems occur when circuit etch lines run in parallel. When board analysis software is not available, the layout must be designed to maintain at least the minimum recommended spacing for bus interfaces:

As a general guideline, the distance between adjacent signals must be a least 3.3 times the distance from signal trace to the nearest return plane. The coupled noise between adjacent traces decreases by the square of the distance between the adjacent traces.

It is also recommended that you specify the height of the above-referenced plane when laying out traces and that you provide this parameter to the PCB manufacturer. By moving traces closer to the nearest reference plane, the coupled noise decreases by the square of the distance to the reference plane.

These design guidelines are illustrated in Figure 5:

Figure 6. Crosstalk Effects on Trace Distance and Height

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Reduce Crosstalk:

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

- Maximize P

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

aggressor

 

victim

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Reference Plane

A9259-01

Additional crosstalk guidelines include the following:

Avoid slots in the ground plane. Slots increase mutual inductance and thus increase crosstalk.

Ensure that the ground plane surrounding the connector-pin fields is not completely cleared out. When the area around the connector pins is completely cleared out, all the return current must flow together around the pin field, increasing crosstalk. The preferred method of laying out a connector in the GND layer is shown in Figure 7.

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Intel® 31154 133 MHz PCI Bridge Design Guide Design Guide

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Contents Intel 31154 133 MHz PCI Bridge Design Guide Design GuideIntel 31154 133 MHz PCI Bridge Design Guide Contents Figures TablesContents Revision History Date Revision Description001 Initial release About This Document Terminology and DefinitionsTerminology and Definition Sheet 1 DefinitionTerminology and Definition Sheet 2 TermISI SHBPCI-to-PCI Bridge Configurations Introduction2Product Overview Intel 31154 133 MHz PCI Bridge ApplicationsFeatures List Features ListRelated External Specifications ReferencesThis page Intentionally Left Blank Package Information Intel 31154 133 MHz PCI Bridge Package Intel 31154 133 MHz PCI Bridge Ball Map-Top View, Left Side Intel 31154 133 MHz PCI Bridge Ball Map-Top View, Right Side Total Signal Count Total Signal CountInterface Signals JtagThis page Intentionally Left Blank Terminations4 Pull-Up/Pull-Down Terminations Sheet 1Secondary PCI Signals Pull-Up/Pull-Down Terminations Sheet 2Pull-Up/Pull-Down Terminations Sheet 3 PCI ClocksPull-Up/Pull-Down Terminations Sheet 4 Hot SwapSarbdisable Pull-Up/Pull-Down Terminations Sheet 5Hardware Straps sampled at the edge of PRST# SarblockPull-Up/Pull-Down Terminations Sheet 6 Serial EepromPull-Up/Pull-Down Terminations Sheet 7 VoltagesMiscellaneous Pull-Up/Pull-Down Terminations Sheet 8 RSTV0RSRV1/CRSTEN SM66ENPull-Up/Pull-Down Terminations Sheet 9 NTMASK#This page Intentionally Left Blank PCI/PCI-X Interface PCI/PCI-X Voltage LevelsInterrupt Routing PCI/PCI-X Voltage LevelsIdsel Lines Primary Idsel LineSecondary Idsel Lines CompactPCI* Hot Swap Mode Select Opaque Memory Region EnableSecondary Idsel Masking Secondary Clock ControlPrimary PCI Clocking Mode Secondary PCI Clocking ModePCI-X Initialization Clocking Modes PCI-X Clocking Modes Secondary Bus Frequency InitializationGND Primary-to-Secondary Frequency Limits PCI-X Initialization PatternClock Frequency MHzRouting Guidelines Crosstalk Crosstalk Effects on Trace Distance and HeightPCB Ground Layout Around Connectors EMI ConsiderationsPower Distribution and Decoupling Pins Voltage Capacitor Value NumberDecoupling Recommendations Intel 31154 133 MHz PCI Bridge Decoupling RecommendationsTrace Impedance This page Intentionally Left Blank PCI-X Layout Guidelines Add-in Card Routing ParametersPCI Clock Layout Guidelines #### PCI-X Topology Layout Guidelines PCI-X Slot GuidelinesWiring Lengths for 133 MHz Slot Single Slot at 133 MHzLower AD Bus Upper AD Bus Segment MaximumWiring Lengths for Embedded 133 MHz Design Lower AD Bus Upper AD BusWiring Lengths for 100 MHz Dual-Slot Dual-Slot at 100 MHzWiring Lengths for Embedded 100 MHz Design Wiring Lengths for 66 MHz Quad-Slot Sheet 1 Quad-Slots at 66 MHzW13 W14Wiring Lengths for 66 MHz Quad-Slot Sheet 2 Wiring Lengths for Embedded 66 MHz Design Minimum LengthEmbedded PCI-X Specification Picmg 1.2 Overview PCI-X at 33 MHzAn Example of an ePCI-X System Wiring Lengths for Picmg 1.2 Backplane Segment AD Bus UnitsPCI-X Clock Wiring Lengths for Picmg Backplane Clock Point to PointThis page Intentionally Left Blank Power Considerations Analog Power PinsPower Sequencing Customer Reference Board EepromCustomer Reference Board Stackup Debug Connectors and Logic Analyzer Connectivity10 Probing PCI-X SignalsLogic Analyzer Pod Frame DevselTrdy BE2Irdy AD31 PCI-X Signal Name § § This page Intentionally Left Blank Thermal Solutions Operational PowerVoltage Maximum Power Thermal Solutions References12 Related DocumentsDesign Reference Material Design Reference MaterialReferences