Intel 31154 manual Pull-Up/Pull-Down Terminations Sheet 4, Hot Swap

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Terminations

 

 

 

Table 5.

Pull-Up/Pull-Down Terminations (Sheet 4 of 9)

 

 

 

 

Signal

 

Pull-Up/Pull-Down or Termination (See Note 1)

Comments

 

 

 

 

 

 

When the internal clock of the 31154 is used, pull

 

 

 

high to VCC33 through an external 8.2 Kresistor.

 

 

 

When an external clock source is used, tie to GND

 

 

 

through a 330 external resistor. All secondary

 

S_GCLKOEN

 

clock outputs (S_CLKO[8:0] and S_BRGCLKO)

 

 

 

asynchronously tristate.

 

 

 

When an external clock source is used, tie

 

 

 

S_CLKOEN[3:0] to a stable value. Refer to

 

 

 

S_CLKOEN[3:0], below.

 

 

 

 

 

 

 

These are strapping pins to enable or tristate

NOTE: This strapping is meaningful only when

 

 

S_CLKO[8:0] after reset.

S_GCLKOEN is pulled high.

 

 

• To enable all S_CLKO[8:0], pull each

When external clocks are used, tie S_GCLKOEN

S_CLKOEN[3:0]

 

S_CLKOEN[3:0] pin to 3.3 V through an

low and tie S_CLKOEN[3:0] to some stable value

 

external 8.2 Kresistor.

(0000b, for example).

 

 

 

 

• To selectively disable some of the

 

 

 

S_CLKO[8:0], refer to 31154 Control

 

 

 

Register 2, bits[8:0].

 

 

 

 

 

Hot Swap

 

 

 

 

 

 

 

 

 

For Hot Swap:

 

HS_ENUM#

 

• Connect the interrupt input pin to the host.

 

 

When not using Hot Swap:

 

 

 

 

 

 

• NC (there is a weak internal pull-up).

 

 

 

 

 

 

 

For Hot Swap:

 

HS_LSTAT

 

• Connect to cPCI ejector switch.

 

 

When not using Hot Swap:

 

 

 

 

 

 

• Tie low to GND.

 

 

 

 

 

 

 

For Hot Swap:

 

HS_LED_OUT

 

• Connect to cPCI blue LED.

 

 

When not using Hot Swap:

 

 

 

 

 

 

• NC

 

 

 

 

 

 

 

For Hot Swap:

 

 

 

0 = The 31154 retries any Type 0 configuration

 

 

 

cycles addressed to it until serial ROM

 

 

 

preload has completed (default)

0 = Tie low to GND.

HS_SM

 

1 = The 31154 ignores (causes master abort) any

 

Type 0 configuration cycles addressed to it

1 = Pull high to 3.3 V through an external 8.2 K

 

 

resistor.

 

 

until its serial ROM preload has completed.

 

 

 

When not using Hot Swap:

 

 

 

• Tie low to GND.

 

 

 

 

 

NOTES:

1.The recommended value for pull-up resistors for PCI applications is 5.6 K(note that the minimum value for PCI 3.3 V signaling RMIN = 2.42 K, RTYP = 8.2 K, as per the PCI Local Bus Specification, Revision 2.3, section 4.3.3).

2.The recommended value for pull-up resistors for PCI-X applications is 8.2 K. For PCI-X, the minimum pull-up resistor value is 5 K, as per the PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0b, section 9.7.

3.For plug-in card implementations, the pull-up must be on the motherboard.

4.Connect PVIO and SVIO pull-up resistors to 5 V or 3.3 V power supply through an external resistor—25 (5 V) or

0 (3.3 V), depending on the signaling level of the primary/secondary PCI bus. Refer to the power-sequencing guidelines in Section 8.2 on page 58.

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Intel® 31154 133 MHz PCI Bridge Design Guide Design Guide

Image 22
Contents Intel 31154 133 MHz PCI Bridge Design Guide Design GuideIntel 31154 133 MHz PCI Bridge Design Guide Contents Figures TablesContents Date Revision Description Revision History001 Initial release Terminology and Definition Sheet 1 About This DocumentTerminology and Definitions DefinitionISI Terminology and Definition Sheet 2Term SHBProduct Overview PCI-to-PCI Bridge ConfigurationsIntroduction2 Intel 31154 133 MHz PCI Bridge ApplicationsFeatures List Features ListRelated External Specifications ReferencesThis page Intentionally Left Blank Package Information Intel 31154 133 MHz PCI Bridge Package Intel 31154 133 MHz PCI Bridge Ball Map-Top View, Left Side Intel 31154 133 MHz PCI Bridge Ball Map-Top View, Right Side Interface Signals Total Signal CountTotal Signal Count JtagThis page Intentionally Left Blank Terminations4 Pull-Up/Pull-Down Terminations Sheet 1Secondary PCI Signals Pull-Up/Pull-Down Terminations Sheet 2Pull-Up/Pull-Down Terminations Sheet 3 PCI ClocksPull-Up/Pull-Down Terminations Sheet 4 Hot SwapHardware Straps sampled at the edge of PRST# SarbdisablePull-Up/Pull-Down Terminations Sheet 5 SarblockPull-Up/Pull-Down Terminations Sheet 6 Serial EepromVoltages Pull-Up/Pull-Down Terminations Sheet 7Miscellaneous RSRV1/CRSTEN Pull-Up/Pull-Down Terminations Sheet 8RSTV0 SM66ENPull-Up/Pull-Down Terminations Sheet 9 NTMASK#This page Intentionally Left Blank Interrupt Routing PCI/PCI-X InterfacePCI/PCI-X Voltage Levels PCI/PCI-X Voltage LevelsPrimary Idsel Line Idsel LinesSecondary Idsel Lines Secondary Idsel Masking CompactPCI* Hot Swap Mode SelectOpaque Memory Region Enable Secondary Clock ControlSecondary PCI Clocking Mode Primary PCI Clocking ModePCI-X Initialization Clocking Modes Secondary Bus Frequency Initialization PCI-X Clocking ModesGND Clock Frequency Primary-to-Secondary Frequency LimitsPCI-X Initialization Pattern MHzRouting Guidelines Crosstalk Crosstalk Effects on Trace Distance and HeightPCB Ground Layout Around Connectors EMI ConsiderationsDecoupling Recommendations Power Distribution and DecouplingPins Voltage Capacitor Value Number Intel 31154 133 MHz PCI Bridge Decoupling RecommendationsTrace Impedance This page Intentionally Left Blank PCI-X Layout Guidelines Add-in Card Routing ParametersPCI Clock Layout Guidelines #### PCI-X Topology Layout Guidelines PCI-X Slot GuidelinesLower AD Bus Upper AD Bus Segment Wiring Lengths for 133 MHz SlotSingle Slot at 133 MHz MaximumWiring Lengths for Embedded 133 MHz Design Lower AD Bus Upper AD BusWiring Lengths for 100 MHz Dual-Slot Dual-Slot at 100 MHzWiring Lengths for Embedded 100 MHz Design W13 Wiring Lengths for 66 MHz Quad-Slot Sheet 1Quad-Slots at 66 MHz W14Wiring Lengths for 66 MHz Quad-Slot Sheet 2 Wiring Lengths for Embedded 66 MHz Design Minimum LengthEmbedded PCI-X Specification Picmg 1.2 Overview PCI-X at 33 MHzAn Example of an ePCI-X System Wiring Lengths for Picmg 1.2 Backplane Segment AD Bus UnitsPCI-X Clock Wiring Lengths for Picmg Backplane Clock Point to PointThis page Intentionally Left Blank Power Considerations Analog Power PinsPower Sequencing Customer Reference Board EepromCustomer Reference Board Stackup Debug Connectors and Logic Analyzer Connectivity10 Probing PCI-X SignalsLogic Analyzer Pod Trdy FrameDevsel BE2Irdy AD31 PCI-X Signal Name § § This page Intentionally Left Blank Operational Power Thermal SolutionsVoltage Maximum Power Thermal Solutions Design Reference Material References12Related Documents Design Reference MaterialReferences