Terminations |
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Table 5. |
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Signal |
| Comments | |
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RSTV0 |
| Tie to GND through a 0 Ω external resistor. |
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RSRV1/CRSTEN | Tie to GND through a 0 Ω external resistor. |
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| S_M66EN is meaningful only when S_PCIXCAP is |
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| connected to GND (that is, when the secondary |
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| PCI bus is in legacy PCI mode). |
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| For designs without secondary PCI slot: |
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| • When the secondary PCI devices (and |
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| loading) support 66 MHz PCI bus, pull up to |
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| 3.3 V through an 8.2 KΩ series resistor. |
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S_M66EN |
| • When the secondary PCI devices (and | Refer to |
| loading) do not supports 66 MHz PCI bus, | Specification, Revision 1.0b, Table | |
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| GND this pin. |
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| For designs with secondary PCI slot: |
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| • When the |
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| support 66 MHz PCI bus, GND this pin. |
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| • When the |
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| 66 MHz PCI bus, connect this pin to M66EN |
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| (pin 49B) of the PCI connector. |
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| For designs without secondary PCI slot: |
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| • When there is at least one legacy PCI device |
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| on the secondary PCI bus, tie this pin directly |
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| to GND. |
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| • When there is at least one |
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| supports maximum |
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| the secondary PCI bus, pull down to GND |
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| through a 10 KΩ series resistor. |
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| • When all secondary |
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S_PCIXCAP |
| bus loading) support | Refer to |
| this pin unconnected (except for decoupling | Specification, Revision 1.0b, Table | |
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| capacitor). |
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| For designs with secondary PCI slot: |
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| • When there is at least one |
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| PCI device on the secondary PCI bus, tie this |
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| pin directly to GND. |
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| • Otherwise, connect this pin to PCIXCAP |
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| (pin B38) of the PCI connector (assuming that |
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| the bus loading supports up to |
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| 133 MHz) |
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NOTES:
1.The recommended value for
2.The recommended value for
3.For
4.Connect PVIO and SVIO
0 Ω (3.3 V), depending on the signaling level of the primary/secondary PCI bus. Refer to the
26 | Intel® 31154 133 MHz PCI Bridge Design Guide Design Guide |