Intel 31154 manual Pull-Up/Pull-Down Terminations Sheet 8, RSTV0, RSRV1/CRSTEN, SM66EN, Spcixcap

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Terminations

 

 

 

Table 5.

Pull-Up/Pull-Down Terminations (Sheet 8 of 9)

 

 

 

 

Signal

 

Pull-Up/Pull-Down or Termination (See Note 1)

Comments

 

 

 

 

RSTV0

 

Tie to GND through a 0 external resistor.

 

 

 

 

RSRV1/CRSTEN

Tie to GND through a 0 external resistor.

 

 

 

 

 

 

 

S_M66EN is meaningful only when S_PCIXCAP is

 

 

 

connected to GND (that is, when the secondary

 

 

 

PCI bus is in legacy PCI mode).

 

 

 

For designs without secondary PCI slot:

 

 

 

• When the secondary PCI devices (and

 

 

 

loading) support 66 MHz PCI bus, pull up to

 

 

 

3.3 V through an 8.2 Kseries resistor.

 

S_M66EN

 

• When the secondary PCI devices (and

Refer to PCI-X Addendum to the PCI Local Bus

 

loading) do not supports 66 MHz PCI bus,

Specification, Revision 1.0b, Table 6-1.

 

 

 

 

GND this pin.

 

 

 

For designs with secondary PCI slot:

 

 

 

• When the on-board PCI device does not

 

 

 

support 66 MHz PCI bus, GND this pin.

 

 

 

• When the on-board PCI device does support

 

 

 

66 MHz PCI bus, connect this pin to M66EN

 

 

 

(pin 49B) of the PCI connector.

 

 

 

 

 

 

 

For designs without secondary PCI slot:

 

 

 

• When there is at least one legacy PCI device

 

 

 

on the secondary PCI bus, tie this pin directly

 

 

 

to GND.

 

 

 

• When there is at least one PCI-X device that

 

 

 

supports maximum PCI-X of only 66 MHz on

 

 

 

the secondary PCI bus, pull down to GND

 

 

 

through a 10 Kseries resistor.

 

 

 

• When all secondary PCI-X devices (and the

 

S_PCIXCAP

 

bus loading) support PCI-X 133 MHz, leave

Refer to PCI-X Addendum to the PCI Local Bus

 

this pin unconnected (except for decoupling

Specification, Revision 1.0b, Table 6-1.

 

 

 

 

capacitor).

 

 

 

For designs with secondary PCI slot:

 

 

 

• When there is at least one on-board legacy

 

 

 

PCI device on the secondary PCI bus, tie this

 

 

 

pin directly to GND.

 

 

 

• Otherwise, connect this pin to PCIXCAP

 

 

 

(pin B38) of the PCI connector (assuming that

 

 

 

the bus loading supports up to PCI-X

 

 

 

133 MHz)

 

 

 

 

 

NOTES:

1.The recommended value for pull-up resistors for PCI applications is 5.6 K(note that the minimum value for PCI 3.3 V signaling RMIN = 2.42 K, RTYP = 8.2 K, as per the PCI Local Bus Specification, Revision 2.3, section 4.3.3).

2.The recommended value for pull-up resistors for PCI-X applications is 8.2 K. For PCI-X, the minimum pull-up resistor value is 5 K, as per the PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0b, section 9.7.

3.For plug-in card implementations, the pull-up must be on the motherboard.

4.Connect PVIO and SVIO pull-up resistors to 5 V or 3.3 V power supply through an external resistor—25 (5 V) or

0 (3.3 V), depending on the signaling level of the primary/secondary PCI bus. Refer to the power-sequencing guidelines in Section 8.2 on page 58.

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Intel® 31154 133 MHz PCI Bridge Design Guide Design Guide

Image 26
Contents Intel 31154 133 MHz PCI Bridge Design Guide Design GuideIntel 31154 133 MHz PCI Bridge Design Guide Contents Figures TablesContents 001 Initial release Revision HistoryDate Revision Description Terminology and Definition Sheet 1 About This DocumentTerminology and Definitions DefinitionISI Terminology and Definition Sheet 2Term SHBProduct Overview PCI-to-PCI Bridge ConfigurationsIntroduction2 Intel 31154 133 MHz PCI Bridge ApplicationsFeatures List Features ListRelated External Specifications ReferencesThis page Intentionally Left Blank Package Information Intel 31154 133 MHz PCI Bridge Package Intel 31154 133 MHz PCI Bridge Ball Map-Top View, Left Side Intel 31154 133 MHz PCI Bridge Ball Map-Top View, Right Side Interface Signals Total Signal CountTotal Signal Count JtagThis page Intentionally Left Blank Terminations4 Pull-Up/Pull-Down Terminations Sheet 1Secondary PCI Signals Pull-Up/Pull-Down Terminations Sheet 2Pull-Up/Pull-Down Terminations Sheet 3 PCI ClocksPull-Up/Pull-Down Terminations Sheet 4 Hot SwapHardware Straps sampled at the edge of PRST# SarbdisablePull-Up/Pull-Down Terminations Sheet 5 SarblockPull-Up/Pull-Down Terminations Sheet 6 Serial EepromMiscellaneous Pull-Up/Pull-Down Terminations Sheet 7Voltages RSRV1/CRSTEN Pull-Up/Pull-Down Terminations Sheet 8RSTV0 SM66ENPull-Up/Pull-Down Terminations Sheet 9 NTMASK#This page Intentionally Left Blank Interrupt Routing PCI/PCI-X InterfacePCI/PCI-X Voltage Levels PCI/PCI-X Voltage LevelsSecondary Idsel Lines Idsel LinesPrimary Idsel Line Secondary Idsel Masking CompactPCI* Hot Swap Mode SelectOpaque Memory Region Enable Secondary Clock ControlPCI-X Initialization Clocking Modes Primary PCI Clocking ModeSecondary PCI Clocking Mode GND PCI-X Clocking ModesSecondary Bus Frequency Initialization Clock Frequency Primary-to-Secondary Frequency LimitsPCI-X Initialization Pattern MHzRouting Guidelines Crosstalk Crosstalk Effects on Trace Distance and HeightPCB Ground Layout Around Connectors EMI ConsiderationsDecoupling Recommendations Power Distribution and DecouplingPins Voltage Capacitor Value Number Intel 31154 133 MHz PCI Bridge Decoupling RecommendationsTrace Impedance This page Intentionally Left Blank PCI-X Layout Guidelines Add-in Card Routing ParametersPCI Clock Layout Guidelines #### PCI-X Topology Layout Guidelines PCI-X Slot GuidelinesLower AD Bus Upper AD Bus Segment Wiring Lengths for 133 MHz SlotSingle Slot at 133 MHz MaximumWiring Lengths for Embedded 133 MHz Design Lower AD Bus Upper AD BusWiring Lengths for 100 MHz Dual-Slot Dual-Slot at 100 MHzWiring Lengths for Embedded 100 MHz Design W13 Wiring Lengths for 66 MHz Quad-Slot Sheet 1Quad-Slots at 66 MHz W14Wiring Lengths for 66 MHz Quad-Slot Sheet 2 Wiring Lengths for Embedded 66 MHz Design Minimum LengthEmbedded PCI-X Specification Picmg 1.2 Overview PCI-X at 33 MHzAn Example of an ePCI-X System Wiring Lengths for Picmg 1.2 Backplane Segment AD Bus UnitsPCI-X Clock Wiring Lengths for Picmg Backplane Clock Point to PointThis page Intentionally Left Blank Power Considerations Analog Power PinsPower Sequencing Customer Reference Board EepromCustomer Reference Board Stackup Debug Connectors and Logic Analyzer Connectivity10 Probing PCI-X SignalsLogic Analyzer Pod Trdy FrameDevsel BE2Irdy AD31 PCI-X Signal Name § § This page Intentionally Left Blank Voltage Maximum Power Thermal SolutionsOperational Power Thermal Solutions Design Reference Material References12Related Documents Design Reference MaterialReferences