Intel 31154 manual PCI-X Signal Name

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Debug Connectors and Logic Analyzer Connectivity

Table 27.	Logic Analyzer Pod 5

	Mictor-38 #3 Pin Number Odd Pod	Logic Analyzer Channel Number	PCI-X Signal Name

	6	CLK/16	PAR64

	8	15	AD47

	10	14	AD46

	12	13	AD45

	14	12	AD44

	16	11	AD43

	18	10	AD42

	20	9	AD41

	22	8	AD40

	24	7	AD39

	26	6	AD38

	28	5	AD37

	30	4	AD36

	32	3	AD35

	34	2	AD34

	36	1	AD33

	38	0	AD32

66	Intel® 31154 133 MHz PCI Bridge Design Guide Design Guide

Image 66

Contents Intel 31154 133 MHz PCI Bridge Design Guide Design GuideIntel 31154 133 MHz PCI Bridge Design Guide Contents Figures TablesContents Revision History Date Revision Description001 Initial release Terminology and Definition Sheet 1 About This DocumentTerminology and Definitions DefinitionISI Terminology and Definition Sheet 2Term SHBProduct Overview PCI-to-PCI Bridge ConfigurationsIntroduction2 Intel 31154 133 MHz PCI Bridge ApplicationsFeatures List Features ListRelated External Specifications ReferencesThis page Intentionally Left Blank Package Information Intel 31154 133 MHz PCI Bridge Package Intel 31154 133 MHz PCI Bridge Ball Map-Top View, Left Side Intel 31154 133 MHz PCI Bridge Ball Map-Top View, Right Side Interface Signals Total Signal CountTotal Signal Count JtagThis page Intentionally Left Blank Terminations4 Pull-Up/Pull-Down Terminations Sheet 1Secondary PCI Signals Pull-Up/Pull-Down Terminations Sheet 2Pull-Up/Pull-Down Terminations Sheet 3 PCI ClocksPull-Up/Pull-Down Terminations Sheet 4 Hot SwapHardware Straps sampled at the edge of PRST# SarbdisablePull-Up/Pull-Down Terminations Sheet 5 SarblockPull-Up/Pull-Down Terminations Sheet 6 Serial EepromPull-Up/Pull-Down Terminations Sheet 7 VoltagesMiscellaneous RSRV1/CRSTEN Pull-Up/Pull-Down Terminations Sheet 8RSTV0 SM66ENPull-Up/Pull-Down Terminations Sheet 9 NTMASK#This page Intentionally Left Blank Interrupt Routing PCI/PCI-X InterfacePCI/PCI-X Voltage Levels PCI/PCI-X Voltage LevelsIdsel Lines Primary Idsel LineSecondary Idsel Lines Secondary Idsel Masking CompactPCI* Hot Swap Mode SelectOpaque Memory Region Enable Secondary Clock ControlPrimary PCI Clocking Mode Secondary PCI Clocking ModePCI-X Initialization Clocking Modes PCI-X Clocking Modes Secondary Bus Frequency InitializationGND Clock Frequency Primary-to-Secondary Frequency LimitsPCI-X Initialization Pattern MHzRouting Guidelines Crosstalk Crosstalk Effects on Trace Distance and HeightPCB Ground Layout Around Connectors EMI ConsiderationsDecoupling Recommendations Power Distribution and DecouplingPins Voltage Capacitor Value Number Intel 31154 133 MHz PCI Bridge Decoupling RecommendationsTrace Impedance This page Intentionally Left Blank PCI-X Layout Guidelines Add-in Card Routing ParametersPCI Clock Layout Guidelines #### PCI-X Topology Layout Guidelines PCI-X Slot GuidelinesLower AD Bus Upper AD Bus Segment Wiring Lengths for 133 MHz SlotSingle Slot at 133 MHz MaximumWiring Lengths for Embedded 133 MHz Design Lower AD Bus Upper AD BusWiring Lengths for 100 MHz Dual-Slot Dual-Slot at 100 MHzWiring Lengths for Embedded 100 MHz Design W13 Wiring Lengths for 66 MHz Quad-Slot Sheet 1Quad-Slots at 66 MHz W14Wiring Lengths for 66 MHz Quad-Slot Sheet 2 Wiring Lengths for Embedded 66 MHz Design Minimum LengthEmbedded PCI-X Specification Picmg 1.2 Overview PCI-X at 33 MHzAn Example of an ePCI-X System Wiring Lengths for Picmg 1.2 Backplane Segment AD Bus UnitsPCI-X Clock Wiring Lengths for Picmg Backplane Clock Point to PointThis page Intentionally Left Blank Power Considerations Analog Power PinsPower Sequencing Customer Reference Board EepromCustomer Reference Board Stackup Debug Connectors and Logic Analyzer Connectivity10 Probing PCI-X SignalsLogic Analyzer Pod Trdy FrameDevsel BE2Irdy AD31 PCI-X Signal Name § § This page Intentionally Left Blank Thermal Solutions Operational PowerVoltage Maximum Power Thermal Solutions Design Reference Material References12Related Documents Design Reference MaterialReferences