Intel 31154 manual Debug Connectors and Logic Analyzer Connectivity10, Probing PCI-X Signals

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Debug Connectors and Logic Analyzer Connectivity

Debug Connectors and Logic Analyzer

Connectivity10

10.1Probing PCI-X Signals

To ease the probing and debugging of the PCI-X signals, you are recommended to passively probe the PCI-X bus signals with a logic analyzer. This can be done by placing six AMP* Mictor-38 connectors on the board or by probing the bus with an interposer card such as the

FuturePlus* Systems* FS2007 that works with an Agilent Technologies* logic analyzer.

For ease of debugging the pinout of the AMP* Mictor-38 connectors, the recommended pin-out matches the FuturePlus* Systems* configuration setup, which allows ease of viewing the PCI signals on an Agilent Technologies* logic analyzer. Refer to the following test equipment that is used for this analysis:

Two AMP* 2-767004-2 surface-mount connectors mounted on the target board and routed to the PCI-X local bus

Two Agilent Technologies* E5346A or E5351A high-density adapter cables from FuturePlus* Systems or Agilent Technologies

Four logic analyzer PODS

FS1104 software from FuturePlus* Systems

Equivalent analyzers can be substituted. A FuturePlus* Systems* configuration file with the FS1104 product that matches the pinout is listed in Table 23 through Table 28.

Intel® 31154 133 MHz PCI Bridge Design Guide Design Guide

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Contents Design Guide Intel 31154 133 MHz PCI Bridge Design GuideIntel 31154 133 MHz PCI Bridge Design Guide Contents Tables FiguresContents Date Revision Description Revision History001 Initial release Terminology and Definitions About This DocumentTerminology and Definition Sheet 1 DefinitionTerm Terminology and Definition Sheet 2ISI SHBIntroduction2 PCI-to-PCI Bridge ConfigurationsProduct Overview Intel 31154 133 MHz PCI Bridge ApplicationsFeatures List Features ListReferences Related External SpecificationsThis page Intentionally Left Blank Package Information Intel 31154 133 MHz PCI Bridge Package Intel 31154 133 MHz PCI Bridge Ball Map-Top View, Left Side Intel 31154 133 MHz PCI Bridge Ball Map-Top View, Right Side Total Signal Count Total Signal CountInterface Signals JtagThis page Intentionally Left Blank Pull-Up/Pull-Down Terminations Sheet 1 Terminations4Pull-Up/Pull-Down Terminations Sheet 2 Secondary PCI SignalsPCI Clocks Pull-Up/Pull-Down Terminations Sheet 3Hot Swap Pull-Up/Pull-Down Terminations Sheet 4Pull-Up/Pull-Down Terminations Sheet 5 SarbdisableHardware Straps sampled at the edge of PRST# SarblockSerial Eeprom Pull-Up/Pull-Down Terminations Sheet 6Voltages Pull-Up/Pull-Down Terminations Sheet 7Miscellaneous RSTV0 Pull-Up/Pull-Down Terminations Sheet 8RSRV1/CRSTEN SM66ENNTMASK# Pull-Up/Pull-Down Terminations Sheet 9This page Intentionally Left Blank PCI/PCI-X Voltage Levels PCI/PCI-X InterfaceInterrupt Routing PCI/PCI-X Voltage LevelsPrimary Idsel Line Idsel LinesSecondary Idsel Lines Opaque Memory Region Enable CompactPCI* Hot Swap Mode SelectSecondary Idsel Masking Secondary Clock ControlSecondary PCI Clocking Mode Primary PCI Clocking ModePCI-X Initialization Clocking Modes Secondary Bus Frequency Initialization PCI-X Clocking ModesGND PCI-X Initialization Pattern Primary-to-Secondary Frequency LimitsClock Frequency MHzRouting Guidelines Crosstalk Effects on Trace Distance and Height CrosstalkEMI Considerations PCB Ground Layout Around ConnectorsPins Voltage Capacitor Value Number Power Distribution and DecouplingDecoupling Recommendations Intel 31154 133 MHz PCI Bridge Decoupling RecommendationsTrace Impedance This page Intentionally Left Blank Add-in Card Routing Parameters PCI-X Layout GuidelinesPCI Clock Layout Guidelines #### PCI-X Slot Guidelines PCI-X Topology Layout GuidelinesSingle Slot at 133 MHz Wiring Lengths for 133 MHz SlotLower AD Bus Upper AD Bus Segment MaximumLower AD Bus Upper AD Bus Wiring Lengths for Embedded 133 MHz DesignDual-Slot at 100 MHz Wiring Lengths for 100 MHz Dual-SlotWiring Lengths for Embedded 100 MHz Design Quad-Slots at 66 MHz Wiring Lengths for 66 MHz Quad-Slot Sheet 1W13 W14Wiring Lengths for 66 MHz Quad-Slot Sheet 2 Minimum Length Wiring Lengths for Embedded 66 MHz DesignPCI-X at 33 MHz Embedded PCI-X Specification Picmg 1.2 OverviewAn Example of an ePCI-X System Segment AD Bus Units Wiring Lengths for Picmg 1.2 BackplaneClock Point to Point PCI-X Clock Wiring Lengths for Picmg BackplaneThis page Intentionally Left Blank Analog Power Pins Power ConsiderationsPower Sequencing Eeprom Customer Reference BoardCustomer Reference Board Stackup Probing PCI-X Signals Debug Connectors and Logic Analyzer Connectivity10Logic Analyzer Pod Devsel FrameTrdy BE2Irdy AD31 PCI-X Signal Name § § This page Intentionally Left Blank Operational Power Thermal SolutionsVoltage Maximum Power Thermal Solutions Related Documents References12Design Reference Material Design Reference MaterialReferences