Intel 31154 manual § §

Page 67

Debug Connectors and Logic Analyzer Connectivity

Table 28.

Logic Analyzer Pod 6

 

 

 

 

 

 

 

Mictor-38 Pin Number Even Pod

Logic Analyzer Channel Number

PCI-X Signal Name

 

 

 

 

 

5

CLK/16

Unused

 

 

 

 

 

7

15

AD63

 

 

 

 

 

9

14

AD62

 

 

 

 

 

11

13

AD60

 

 

 

 

 

13

12

AD59

 

 

 

 

 

15

11

AD58

 

 

 

 

 

17

10

AD57

 

 

 

 

 

19

9

AD56

 

 

 

 

 

21

8

AD55

 

 

 

 

 

23

7

AD54

 

 

 

 

 

25

6

AD53

 

 

 

 

 

27

5

AD52

 

 

 

 

 

29

4

AD51

 

 

 

 

 

31

3

AD50

 

 

 

 

 

33

2

AD49

 

 

 

 

 

35

1

AD48

 

 

 

 

 

37

0

AD48

 

 

 

 

The recommended placement of the Mictor connectors is at either end of the bus segment. The Mictors are placed at the end of a stub that must be as short as possible, and are then daisy-chained off either end of the bus. When there is not enough room to place the Mictors at least 0.5" from the target, an alternate method can be used. This alternate method is to place the logic analyzer termination circuitry on the target and then extend the etch from the end of the termination circuitry over to the Mictor connectors. The connection from the Mictors to the logic analyzer must then be made with the E5351A. The E5346A contains the logic analyzer termination circuitry, and the E5351A does not.

§ §

Intel® 31154 133 MHz PCI Bridge Design Guide Design Guide

67

Image 67
Contents Design Guide Intel 31154 133 MHz PCI Bridge Design GuideIntel 31154 133 MHz PCI Bridge Design Guide Contents Tables FiguresContents Date Revision Description Revision History001 Initial release Definition About This DocumentTerminology and Definitions Terminology and Definition Sheet 1SHB Terminology and Definition Sheet 2Term ISIIntel 31154 133 MHz PCI Bridge Applications PCI-to-PCI Bridge ConfigurationsIntroduction2 Product OverviewFeatures List Features ListReferences Related External SpecificationsThis page Intentionally Left Blank Package Information Intel 31154 133 MHz PCI Bridge Package Intel 31154 133 MHz PCI Bridge Ball Map-Top View, Left Side Intel 31154 133 MHz PCI Bridge Ball Map-Top View, Right Side Jtag Total Signal CountTotal Signal Count Interface SignalsThis page Intentionally Left Blank Pull-Up/Pull-Down Terminations Sheet 1 Terminations4Pull-Up/Pull-Down Terminations Sheet 2 Secondary PCI SignalsPCI Clocks Pull-Up/Pull-Down Terminations Sheet 3Hot Swap Pull-Up/Pull-Down Terminations Sheet 4Sarblock SarbdisablePull-Up/Pull-Down Terminations Sheet 5 Hardware Straps sampled at the edge of PRST#Serial Eeprom Pull-Up/Pull-Down Terminations Sheet 6Voltages Pull-Up/Pull-Down Terminations Sheet 7Miscellaneous SM66EN Pull-Up/Pull-Down Terminations Sheet 8RSTV0 RSRV1/CRSTENNTMASK# Pull-Up/Pull-Down Terminations Sheet 9This page Intentionally Left Blank PCI/PCI-X Voltage Levels PCI/PCI-X InterfacePCI/PCI-X Voltage Levels Interrupt RoutingPrimary Idsel Line Idsel LinesSecondary Idsel Lines Secondary Clock Control CompactPCI* Hot Swap Mode SelectOpaque Memory Region Enable Secondary Idsel MaskingSecondary PCI Clocking Mode Primary PCI Clocking ModePCI-X Initialization Clocking Modes Secondary Bus Frequency Initialization PCI-X Clocking ModesGND MHz Primary-to-Secondary Frequency LimitsPCI-X Initialization Pattern Clock FrequencyRouting Guidelines Crosstalk Effects on Trace Distance and Height CrosstalkEMI Considerations PCB Ground Layout Around ConnectorsIntel 31154 133 MHz PCI Bridge Decoupling Recommendations Power Distribution and DecouplingPins Voltage Capacitor Value Number Decoupling RecommendationsTrace Impedance This page Intentionally Left Blank Add-in Card Routing Parameters PCI-X Layout GuidelinesPCI Clock Layout Guidelines #### PCI-X Slot Guidelines PCI-X Topology Layout GuidelinesMaximum Wiring Lengths for 133 MHz SlotSingle Slot at 133 MHz Lower AD Bus Upper AD Bus SegmentLower AD Bus Upper AD Bus Wiring Lengths for Embedded 133 MHz DesignDual-Slot at 100 MHz Wiring Lengths for 100 MHz Dual-SlotWiring Lengths for Embedded 100 MHz Design W14 Wiring Lengths for 66 MHz Quad-Slot Sheet 1Quad-Slots at 66 MHz W13Wiring Lengths for 66 MHz Quad-Slot Sheet 2 Minimum Length Wiring Lengths for Embedded 66 MHz DesignPCI-X at 33 MHz Embedded PCI-X Specification Picmg 1.2 OverviewAn Example of an ePCI-X System Segment AD Bus Units Wiring Lengths for Picmg 1.2 BackplaneClock Point to Point PCI-X Clock Wiring Lengths for Picmg BackplaneThis page Intentionally Left Blank Analog Power Pins Power ConsiderationsPower Sequencing Eeprom Customer Reference BoardCustomer Reference Board Stackup Probing PCI-X Signals Debug Connectors and Logic Analyzer Connectivity10Logic Analyzer Pod BE2 FrameDevsel TrdyIrdy AD31 PCI-X Signal Name § § This page Intentionally Left Blank Operational Power Thermal SolutionsVoltage Maximum Power Thermal Solutions Design Reference Material References12Related Documents Design Reference MaterialReferences