Terminations |
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Table 5. |
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Signal |
| Comments | ||
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P_GNT# |
| Connect to GNT# of the primary PCI bus. |
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| Connect to one of the AD lines of the primary PCI | Refer to Section 5.3, “IDSEL Lines” on page 30 for | |
P_IDSEL# |
| bus or to the IDSEL# signal of the PCI edge | ||
| more details. | |||
|
| connector (for | ||
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P_M66EN |
| Connect to the M66EN signal of the primary PCI |
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| bus of the PCI |
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P_PAR |
| Connect to PAR of the primary PCI bus. |
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P_PAR64 |
| Connect to PERR# of the primary PCI bus. |
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P_PERR# |
| Connect to PERR# of the primary PCI bus. |
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P_REQ# |
| Connect to one of the PCI bus request signals of |
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| the primary PCI bus. |
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P_SERR# |
| Connect to SERR# of the primary PCI bus. |
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Secondary PCI Signals |
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S_AD[63:32] |
| Pull up to VCC33 through external 8.2 KΩ |
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| resistors. |
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S_CBE[7:4]# |
| Pull up to VCC33 through external 8.2 KΩ |
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| resistors. |
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S_REQ64# |
| Pull up to VCC33 through external 8.2 KΩ |
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| resistors. |
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S_ACK64# |
| Pull up to VCC33 through external 8.2 KΩ |
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| resistors. |
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S_FRAME#, |
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S_IRDY#, |
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S_TRDY#, |
| Pull up to VCC33 voltage through external 8.2 KΩ |
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S_STOP#, |
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| resistors. |
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S_DEVSEL#, |
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S_PERR#, |
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S_SERR# |
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S_REQ[8:1]#, |
| Pull up to VCC33 voltage through external 8.2 KΩ |
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S_REQ0#/BR_GNT#, | ||||
resistors. | ||||
S_GNT0#/BR_REQ# |
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Secondary GNT# |
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S_GNT1#, |
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S_GNT2#, |
| Connect to GNT# input of the PCI devices on the |
| |
S_GNT3#, |
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| secondary PCI bus. |
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S_GNT4#, |
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S_GNT5#, |
| NC when not used. |
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S_GNT6#, |
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S_GNT7#, |
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S_GNT8# |
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NOTES:
1.The recommended value for
2.The recommended value for
3.For
4.Connect PVIO and SVIO
0 Ω (3.3 V), depending on the signaling level of the primary/secondary PCI bus. Refer to the
20 | Intel® 31154 133 MHz PCI Bridge Design Guide Design Guide |