Intel 31154 manual Pull-Up/Pull-Down Terminations Sheet 2, Secondary PCI Signals

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Terminations

 

 

 

Table 5.

Pull-Up/Pull-Down Terminations (Sheet 2 of 9)

 

 

 

 

Signal

 

Pull-Up/Pull-Down or Termination (See Note 1)

Comments

 

 

 

 

P_GNT#

 

Connect to GNT# of the primary PCI bus.

 

 

 

 

 

 

 

Connect to one of the AD lines of the primary PCI

Refer to Section 5.3, “IDSEL Lines” on page 30 for

P_IDSEL#

 

bus or to the IDSEL# signal of the PCI edge

 

more details.

 

 

connector (for add-in card applications).

 

 

 

 

 

 

 

P_M66EN

 

Connect to the M66EN signal of the primary PCI

 

 

bus of the PCI add-in card finger.

 

 

 

 

 

 

 

 

P_PAR

 

Connect to PAR of the primary PCI bus.

 

 

 

 

 

P_PAR64

 

Connect to PERR# of the primary PCI bus.

 

 

 

 

 

P_PERR#

 

Connect to PERR# of the primary PCI bus.

 

 

 

 

 

P_REQ#

 

Connect to one of the PCI bus request signals of

 

 

the primary PCI bus.

 

 

 

 

 

 

 

 

P_SERR#

 

Connect to SERR# of the primary PCI bus.

 

 

 

 

Secondary PCI Signals

 

 

 

 

 

S_AD[63:32]

 

Pull up to VCC33 through external 8.2 K

 

 

resistors.

 

 

 

 

 

 

 

 

S_CBE[7:4]#

 

Pull up to VCC33 through external 8.2 K

 

 

resistors.

 

 

 

 

 

 

 

 

S_REQ64#

 

Pull up to VCC33 through external 8.2 K

 

 

resistors.

 

 

 

 

 

 

 

 

S_ACK64#

 

Pull up to VCC33 through external 8.2 K

 

 

resistors.

 

 

 

 

 

 

 

 

S_FRAME#,

 

 

 

S_IRDY#,

 

 

 

S_TRDY#,

 

Pull up to VCC33 voltage through external 8.2 K

 

S_STOP#,

 

 

 

resistors.

 

S_DEVSEL#,

 

 

 

 

 

S_PERR#,

 

 

 

S_SERR#

 

 

 

 

 

 

 

S_REQ[8:1]#,

 

Pull up to VCC33 voltage through external 8.2 K

 

S_REQ0#/BR_GNT#,

Pull-up for both internal and external arbiter mode.

resistors.

S_GNT0#/BR_REQ#

 

 

 

 

 

 

Secondary GNT#

 

 

S_GNT1#,

 

 

 

S_GNT2#,

 

Connect to GNT# input of the PCI devices on the

 

S_GNT3#,

 

 

 

secondary PCI bus.

 

S_GNT4#,

 

 

 

 

 

S_GNT5#,

 

NC when not used.

 

S_GNT6#,

 

 

 

S_GNT7#,

 

 

 

S_GNT8#

 

 

 

 

 

 

 

NOTES:

1.The recommended value for pull-up resistors for PCI applications is 5.6 K(note that the minimum value for PCI 3.3 V signaling RMIN = 2.42 K, RTYP = 8.2 K, as per the PCI Local Bus Specification, Revision 2.3, section 4.3.3).

2.The recommended value for pull-up resistors for PCI-X applications is 8.2 K. For PCI-X, the minimum pull-up resistor value is 5 K, as per the PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0b, section 9.7.

3.For plug-in card implementations, the pull-up must be on the motherboard.

4.Connect PVIO and SVIO pull-up resistors to 5 V or 3.3 V power supply through an external resistor—25 (5 V) or

0 (3.3 V), depending on the signaling level of the primary/secondary PCI bus. Refer to the power-sequencing guidelines in Section 8.2 on page 58.

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Intel® 31154 133 MHz PCI Bridge Design Guide Design Guide

Image 20
Contents Intel 31154 133 MHz PCI Bridge Design Guide Design GuideIntel 31154 133 MHz PCI Bridge Design Guide Contents Figures TablesContents 001 Initial release Revision HistoryDate Revision Description About This Document Terminology and DefinitionsTerminology and Definition Sheet 1 DefinitionTerminology and Definition Sheet 2 TermISI SHBPCI-to-PCI Bridge Configurations Introduction2Product Overview Intel 31154 133 MHz PCI Bridge ApplicationsFeatures List Features ListRelated External Specifications ReferencesThis page Intentionally Left Blank Package Information Intel 31154 133 MHz PCI Bridge Package Intel 31154 133 MHz PCI Bridge Ball Map-Top View, Left Side Intel 31154 133 MHz PCI Bridge Ball Map-Top View, Right Side Total Signal Count Total Signal CountInterface Signals JtagThis page Intentionally Left Blank Terminations4 Pull-Up/Pull-Down Terminations Sheet 1Secondary PCI Signals Pull-Up/Pull-Down Terminations Sheet 2Pull-Up/Pull-Down Terminations Sheet 3 PCI ClocksPull-Up/Pull-Down Terminations Sheet 4 Hot SwapSarbdisable Pull-Up/Pull-Down Terminations Sheet 5Hardware Straps sampled at the edge of PRST# SarblockPull-Up/Pull-Down Terminations Sheet 6 Serial EepromMiscellaneous Pull-Up/Pull-Down Terminations Sheet 7Voltages Pull-Up/Pull-Down Terminations Sheet 8 RSTV0RSRV1/CRSTEN SM66ENPull-Up/Pull-Down Terminations Sheet 9 NTMASK#This page Intentionally Left Blank PCI/PCI-X Interface PCI/PCI-X Voltage LevelsInterrupt Routing PCI/PCI-X Voltage LevelsSecondary Idsel Lines Idsel LinesPrimary Idsel Line CompactPCI* Hot Swap Mode Select Opaque Memory Region EnableSecondary Idsel Masking Secondary Clock ControlPCI-X Initialization Clocking Modes Primary PCI Clocking ModeSecondary PCI Clocking Mode GND PCI-X Clocking ModesSecondary Bus Frequency Initialization Primary-to-Secondary Frequency Limits PCI-X Initialization PatternClock Frequency MHzRouting Guidelines Crosstalk Crosstalk Effects on Trace Distance and HeightPCB Ground Layout Around Connectors EMI ConsiderationsPower Distribution and Decoupling Pins Voltage Capacitor Value NumberDecoupling Recommendations Intel 31154 133 MHz PCI Bridge Decoupling RecommendationsTrace Impedance This page Intentionally Left Blank PCI-X Layout Guidelines Add-in Card Routing ParametersPCI Clock Layout Guidelines #### PCI-X Topology Layout Guidelines PCI-X Slot GuidelinesWiring Lengths for 133 MHz Slot Single Slot at 133 MHzLower AD Bus Upper AD Bus Segment MaximumWiring Lengths for Embedded 133 MHz Design Lower AD Bus Upper AD BusWiring Lengths for 100 MHz Dual-Slot Dual-Slot at 100 MHzWiring Lengths for Embedded 100 MHz Design Wiring Lengths for 66 MHz Quad-Slot Sheet 1 Quad-Slots at 66 MHzW13 W14Wiring Lengths for 66 MHz Quad-Slot Sheet 2 Wiring Lengths for Embedded 66 MHz Design Minimum LengthEmbedded PCI-X Specification Picmg 1.2 Overview PCI-X at 33 MHzAn Example of an ePCI-X System Wiring Lengths for Picmg 1.2 Backplane Segment AD Bus UnitsPCI-X Clock Wiring Lengths for Picmg Backplane Clock Point to PointThis page Intentionally Left Blank Power Considerations Analog Power PinsPower Sequencing Customer Reference Board EepromCustomer Reference Board Stackup Debug Connectors and Logic Analyzer Connectivity10 Probing PCI-X SignalsLogic Analyzer Pod Frame DevselTrdy BE2Irdy AD31 PCI-X Signal Name § § This page Intentionally Left Blank Voltage Maximum Power Thermal SolutionsOperational Power Thermal Solutions References12 Related DocumentsDesign Reference Material Design Reference MaterialReferences