Intel 31154 manual PCI-X Layout Guidelines, Add-in Card Routing Parameters

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PCI-X Layout Guidelines

PCI-X Layout Guidelines

7

 

 

For acceptable signal integrity with bus speeds up to 133 MHz, it is important for the PCB design layout to have controlled impedance.

The list below provides general guidelines for routing your PCI bus signals:

Avoid routing signal traces longer than 8".

All clock nets must be on the top layer.

All 32-bit interface signals from the PCI edge fingers must be no longer than 1.5" and no shorter than 0.75".

All 64-bit extension signals from the PCI edge fingers must be no longer than 2.75" and no shorter than 1.75".

P_CLK from the PCI edge finger must be 2.5" ± 0.1".

P_RST# from the PCI edge finger must be no longer than 3.0" and no shorter than 0.75".

Table 12 provides information on maximum lengths for routing add-on card signals.

Table 12.

Add-in Card Routing Parameters

 

 

 

 

 

 

 

 

PCI-X

 

 

Parameter

 

 

 

Minimum

 

Maximum

 

 

Length

 

Length

 

 

(inches)

 

(inches)

 

 

 

 

 

 

P_CLK

2.40

 

2.60

 

 

 

 

 

 

P_AD[31:0]

0.75

 

1.50

 

 

 

 

 

 

P_AD[63:32]

1.75

 

2.75

 

 

 

 

 

 

P_RST#

0.75

 

3.00

 

 

 

 

 

Note: Do not use more than one via for the primary PCI bus signals.

Intel® 31154 133 MHz PCI Bridge Design Guide Design Guide

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Contents Design Guide Intel 31154 133 MHz PCI Bridge Design GuideIntel 31154 133 MHz PCI Bridge Design Guide Contents Tables FiguresContents 001 Initial release Revision HistoryDate Revision Description Terminology and Definitions About This DocumentTerminology and Definition Sheet 1 DefinitionTerm Terminology and Definition Sheet 2ISI SHBIntroduction2 PCI-to-PCI Bridge ConfigurationsProduct Overview Intel 31154 133 MHz PCI Bridge ApplicationsFeatures List Features ListReferences Related External SpecificationsThis page Intentionally Left Blank Package Information Intel 31154 133 MHz PCI Bridge Package Intel 31154 133 MHz PCI Bridge Ball Map-Top View, Left Side Intel 31154 133 MHz PCI Bridge Ball Map-Top View, Right Side Total Signal Count Total Signal CountInterface Signals JtagThis page Intentionally Left Blank Pull-Up/Pull-Down Terminations Sheet 1 Terminations4Pull-Up/Pull-Down Terminations Sheet 2 Secondary PCI SignalsPCI Clocks Pull-Up/Pull-Down Terminations Sheet 3Hot Swap Pull-Up/Pull-Down Terminations Sheet 4Pull-Up/Pull-Down Terminations Sheet 5 SarbdisableHardware Straps sampled at the edge of PRST# SarblockSerial Eeprom Pull-Up/Pull-Down Terminations Sheet 6Miscellaneous Pull-Up/Pull-Down Terminations Sheet 7Voltages RSTV0 Pull-Up/Pull-Down Terminations Sheet 8RSRV1/CRSTEN SM66ENNTMASK# Pull-Up/Pull-Down Terminations Sheet 9This page Intentionally Left Blank PCI/PCI-X Voltage Levels PCI/PCI-X InterfaceInterrupt Routing PCI/PCI-X Voltage LevelsSecondary Idsel Lines Idsel LinesPrimary Idsel Line Opaque Memory Region Enable CompactPCI* Hot Swap Mode SelectSecondary Idsel Masking Secondary Clock ControlPCI-X Initialization Clocking Modes Primary PCI Clocking ModeSecondary PCI Clocking Mode GND PCI-X Clocking ModesSecondary Bus Frequency Initialization PCI-X Initialization Pattern Primary-to-Secondary Frequency LimitsClock Frequency MHzRouting Guidelines Crosstalk Effects on Trace Distance and Height CrosstalkEMI Considerations PCB Ground Layout Around ConnectorsPins Voltage Capacitor Value Number Power Distribution and DecouplingDecoupling Recommendations Intel 31154 133 MHz PCI Bridge Decoupling RecommendationsTrace Impedance This page Intentionally Left Blank Add-in Card Routing Parameters PCI-X Layout GuidelinesPCI Clock Layout Guidelines #### PCI-X Slot Guidelines PCI-X Topology Layout GuidelinesSingle Slot at 133 MHz Wiring Lengths for 133 MHz SlotLower AD Bus Upper AD Bus Segment MaximumLower AD Bus Upper AD Bus Wiring Lengths for Embedded 133 MHz DesignDual-Slot at 100 MHz Wiring Lengths for 100 MHz Dual-SlotWiring Lengths for Embedded 100 MHz Design Quad-Slots at 66 MHz Wiring Lengths for 66 MHz Quad-Slot Sheet 1W13 W14Wiring Lengths for 66 MHz Quad-Slot Sheet 2 Minimum Length Wiring Lengths for Embedded 66 MHz DesignPCI-X at 33 MHz Embedded PCI-X Specification Picmg 1.2 OverviewAn Example of an ePCI-X System Segment AD Bus Units Wiring Lengths for Picmg 1.2 BackplaneClock Point to Point PCI-X Clock Wiring Lengths for Picmg BackplaneThis page Intentionally Left Blank Analog Power Pins Power ConsiderationsPower Sequencing Eeprom Customer Reference BoardCustomer Reference Board Stackup Probing PCI-X Signals Debug Connectors and Logic Analyzer Connectivity10Logic Analyzer Pod Devsel FrameTrdy BE2Irdy AD31 PCI-X Signal Name § § This page Intentionally Left Blank Voltage Maximum Power Thermal SolutionsOperational Power Thermal Solutions Related Documents References12Design Reference Material Design Reference MaterialReferences