KS152JB Universal Communications Controller Technical Specifications
values are polled only in the next machine cycle. If a request is active and all three conditions are met, then the hardware generated LCALL is executed. This call itself takes two machine cycles to be completed. Thus there is a minimum time of three machine cycles between the interrupt flag being set and the interrupt service routine being executed.
A longer response time should be anticipated if any of the three conditions are not met. If a higher or equal priority is being serviced, then the interrupt latency time obviously depends on the nature of the service routine currently being executed. If the polling cycle is not the last machine cycle of the instruction being executed, then an additional delay is introduced. This is maximum in the case of MUL and DIV instructions which are four machine cycles long. In case of a RETI or a write to IP or IE registers the delay can be at most 5 machine cycles. This is because at most one cycle is needed to complete the current instruction and at most 4 machine cycles to execute the next instruction, which may be a MUL or DIV instruction.
Thus in a
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