Kawasaki 80C152, 80C51 technical specifications Kawasaki LSI USA, Inc Ver .9 KS152JB2

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KS152JB Universal Communications Controller Technical Specifications

registers. On the DMA channel servicing the receiver, the control register needs to be loaded as follows: DCONn.2 = 0, this sets the transfer mode so that response is to GSC interrupts and put the DMA control in alternate cycle mode; DCONn.3 = 1, this enables the demand mode; DCONn.4 = 0, this clears the automatic increment option for the source address; and DCONn.5 = 1, this defines the source as SFR, The DMA channel servicing the receiver also needs its source address register to contain the address of RFIFO (SHRHN = XXH, SARLN = 0F4H). On the DMA channel servicing the transmitter, the control register needs to be loaded as follows: DCONn.2 = 0; DCONn.3 = 1; DCONn.6 = 0, this clears the automatic increment option for the destination address; and DCONn.7 = 1, this sets the destination as SFR. The DMA channel serv- ing the transmitter also requires that its destination address register contains the address of TFIFO (DARHN = XXH, DARLN = 85H). Assuming that DCON0 would be serving the receiver and DCON1 the transmitter, DCON0 would be loaded with XX1010X0B. The contents of SARH0 and DARH1 do not have any impact when using internal SFRs as the source or destination.

When using the DMA channels to service the GSC, the byte count registers will also need to be initialized.

The Done flag for the DMA channel servicing the receiver should be used if fixed packet lengths only are being transmitted or to insure that memory is not over-written by long received data packets. Overwriting of data can occur when using a smaller buffer than the packet size. In these cases the servicing of the DMA and/or GSC would be in response to the DMA Done flag when the byte count reaches zero.

In some cases the buffer size is not the limiting factor and the packet length will be unknown. in these cases it would be desirable to eliminate the function of the Done flag. To effectively disable the Done flag for the DMA channel servicing the receiver, the byte count should be set to some number larger than any packet that will be received, up to 64K. If not using the Done flag, then GSC servicing would be driven by the receive Done (RDN) flag and /or interrupt. RDN is set when the EOF is detected. When using the RDN flag, RFNE should also be checked to insure that all the data has been emptied out of the receive FIFO.

The byte count register is used for all transmissions and this means that all packets going out will have to be of the same length or the length of the packet to be sent will have to be known prior to the start of transmission. When using the DMA channels to service the GSC transmitter, there is no practical way to disable the Done flag. This is because the transmit done flag (TDN) is set when the transmit FIFO is empty and the last message bit has been transmitted. But, when using the DMA channel to service the transmitter, loads to the TFIFO continue to occur until the byte count reaches 0. This makes it impossible to use TDN as a flag to stop the DMA transfers to TFIFO. It is possible to examine some other registers or conditions, such as the current byte count, to determine when to stop the DMA transfers to TFIFO, but this is not recommended as a way to service the DMA and GSC when transmitting because frequent reading of the DMA regis- ters will cause the effective DMA transfer rate to slow down.

When using the DMA channels, initialization of the GSC would be exactly the same as normal except that TSTAT.0 = 1 (DMA), this informs the GSC that the DMA channels are going to be used to service the GSC. Although only TSTAT is written to, both the receiver and transmitter use

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Ver. 0.9 KS152JB2

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Contents Introduction Technical Specifications PIN Description Pin DescriptionName Description Port Pin Name Alternate FunctionXTAL1 XTAL2RST Psen ALEEben EpsenSFR map for the cpu Special function RegistersReset Timing Reset Values of the SFRs Scon ConfigurationsSbuf Indeterminate Tmod PconPort bit I/O Pads Port 0 I/O Pad Port 2 I/O PadPorts 4,5 Psen Epsen ProgramComments Fetch viaTmod Timer/Counter Mode Control Register TIMER/COUNTERSMode Tcon Timer/Counter Control RegisterTimer/Counter in Mode Timer/Counter 0 in Mode IE Interrupt Enable RegisterInterrupts Priority Level Structure Pgste PDMA1 Pgstv PDMA0 Pgsre Pgsrv Egste EDMA1 Egstv EDMA0 Egsre EgsrvEX0 PX0Pgsrv Egsrv 2BHEDMA1 PDMA1PT1 ET1 1BHKawasaki LSI USA, Inc Ver .9 KS152JB2 Power Down and Idle Status of the External Pins during Idle and Power DownALE Psen Smod IDL Pcon Power Control RegisterLocal Serial Channel Controller Local Serial Port ModeSerial Port Mode Mode Load Sbuf Baud Rates Timer 1 generated commonly used Baud rates SmodMHZ SINGLE-STEP Operation JNBReti Kawasaki LSI USA Inc Introduction Global Serial ChannelDC JAM CRC 11/IDLE CRC None11/IDLE Csma SdlcExternal clock Internal clock Control cpu Control dma Raw Receive Raw Transmit CSMA/CD Overview CSMA/CD Frame FormatPreamble BOF Address Info CRC EOF Kawasaki LSI USA, Inc Ver .9 KS152JB2 23 24 Interframe Space Manchester Encoding BIT Time CSMA/CD Data EncodingCollision Detection Jitter ToleranceNarrow Pulses Missing 0-to-1 TransitionUnexpected 1-to-0 Transition GSC Inactive Resolution of CollisionsResponse to a Detected Collision What the GSC was doing TfifoBackoff DCRAlgorithm Random Backoff Prbs Tcdcnt Load Bkoff Slot Clock MyslotBKOFF= Myslot Deterministic Backoff Hardware Based Acknowledge Kawasaki LSI USA, Inc Ver .9 KS152JB2 BOF Address Control Info CRC EOF Sdlc Frame FormatKawasaki LSI USA, Inc Ver .9 KS152JB2 Data Encoding Nrzi BIT TimeBIT STUFFING/STRIPPING Sending Abort Character Line IdleAcknowledgement Point-to-point Network PRIMARY/SECONDARY StationsMulti-Drop Network Ring NetworkHDLC/SDLC Comparison Using a Preamble in SdlcSdlc Hdlc User Defined ProtocolsPlanning for Network Changes and Expansions Line DisciplineDMA Servicing of GSC Channels Kawasaki LSI USA, Inc Ver .9 KS152JB2 Baud Rate Initialization External Driver Interface Test ModesJitter Receive Receive Sampling Rate Received Local Value Manchester Encoding BIT TimeBIT Time Received Transmit WaveformsCSMA/CD Clock Recovery Receiver Clock RecoveryExternal Clocking Determining Receiver ErrorsRcbat Crce Addressing2 CPU/DMA Control of the GSC Determining Line DisciplineCollisions and Backoff What the GSC was doing Response Successful Ending of Transmissions and Receptions GSC Register DescriptionsPL1 PL0 Length Bits GMOD84H Xtclk PL1 PL0Kawasaki LSI USA, Inc Ver .9 KS152JB2 ARB REQ Garen Xrclk Gfien IDL DCJ DCR SA5 SA4 SA3 SA2 SA1 SA0Rcabt Crce RDN Rfne Gren Haben Kawasaki LSI USA, Inc Ver .9 KS152JB2 LNI Noack Tcdt TDN Tfnf TEN DMA Kawasaki LSI USA, Inc Ver .9 KS152JB2 DMA with the 80C152 DMA OperationDMA Registers Burst Mode Alternate Cycle ModeDAS IDA SAS ISAExternal Demand Mode Serial Port Demand Mode12 OSC.PERIODS ALE Psen P1 Inst Float Timing DiagramsPCH P2 SFR DMA Cycle Resume Program Execution DMA Transfer from Internal Memory to Internal Memory12 OSC. Periods ALE Psen Inst DMA Data OUT PCL Inst PCH DMA Cycle 12 OSC. Periods Resume Program Execution ALE PsenDMA Cycle Resume Program Execution Request Mode Arbiter ModeHold/Hold Acknowledge ARB REQ Using the HOLD/HLDA AcknowledgeALE ARB If Hlda = ALE AEQ ALE REQ Internal Logic of the ArbiterDmxrq Internal Logic of the Requester DMA Arbitration Kawasaki LSI USA, Inc.oup, Inc Ver .9 KS152JB2 Kawasaki LSI USA, Inc Ver .9 KS152JB2 Kawasaki LSI USA, Inc Ver .9 KS152JB2 DMA Arbitration with Hold/Hold Ack DAS IDA SAS ISA Done Summary of DMA Control BitsInterrupt Structure IE0 ET1 EX1 ET0 EX0 TI+RIIPN1 PT1 PX1 PT0 PX0Transmit Error Flags Logic for Clearing TEN, Setting TDN GSC Transmitter Error ConditionsGSC Receiver Error Conditions Glossary Kawasaki LSI USA, Inc Ver .9 KS152JB2 DCON0/1 092H,093H Xtclk PL1 PL0 Kawasaki LSI USA, Inc 102 Ver .9 KS152JB2 Kawasaki LSI USA, Inc 103 Ver .9 KS152JB2 PT1 PX1 PT0 EX0 Myslot 0F5H DCJ DCR SA5 SA4 SA3 SA2 SA1 SA0 Smod ARB REQ Garen Xrclk Gfien IDL OVR Rcabt Crce RDN Rfne Gren Haben Kawasaki LSI USA, Inc 108 Ver .9 KS152JB2 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 SM0 SM1 SM2 REN TB8 RB8Gate Kawasaki LSI USA, Inc 111 Ver .9 KS152JB2 Stack Pointer PortData Pointer LOW DPL.7 DPL.6 DPL5 DPL.4 DPL.3 DPL.2 DPL.1 DPL.0Data Pointer High Timer ControlDPH.7 DPH.6 DPH.5 DPH.4 DPH.3 DPH.2 DPH.1 DPH.0 DPHGate Timer Timer Mode ControlTimer 0 LSB Timer 1 LSBTimer 1 MSB Timer 0 MSBSM0 Serial Port ControlSerial Data Buffer SBUF.7RS1 RS0 Program Status WordACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0 AccumulatorKawasaki LSI USA, Inc 119 Ver .9 KS152JB2 Kawasaki LSI USA, Inc 120 Ver .9 KS152JB2
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