Kawasaki 80C51, 80C152 technical specifications Kawasaki LSI USA, Inc Ver .9 KS152JB2

Page 38

KS152JB Universal Communications Controller Technical Specifications

PREAMBLE - The preamble is a series of alternating 1s and 0s. The length of the preamble is programmable to be 0, 8, 32, or 64 bits. The purpose of the preamble is to allow all the receivers to synchronize to the same clock edges and identifies to the other stations on-line that there is activity indicating the link is being used. For these reasons zero preamble length is not compatible with standard CSMA/CD, protocols. When using CSMA/CD, the BOF is considered part of the preamble compared to SDLC, where the BOF is not part of the preamble. This means that if zero preamble length were to be used in CSMA/CD, mode, no BOF would be generated. It is strongly recommended that zero preamble length never be used in CSMA/CD mode. If the preamble con- tains two consecutive 0s, The preamble is considered invalid. If the C152 detects an invalid pre- amble, the frame is ignored.

BOF - In CSMA/CD the Beginning -Of-Frame is a part of the preamble and consists of two sequential 1s. The purpose of the BOF is to identify the end of the preamble and indicate to the receiver(s) that the address will immediately follow.

ADDRESS - The address field is used to identify which messages are intended for which stations. The user must assign addresses to each destination and source. How the addresses are assigned, how they are maintained, and how each transmitter is made aware of which addresses are avail- able is an issue that is left to the user. Some suggestions are discussed in Section 3.5.5. Generally, each address is unique to each station but there are special cases where this is not true. In these special cases a message is intended for more than one station. These multi-targeted messages are called broadcast or multicast-group address usually is indicated by using a 1 as the first address bit. The user can choose to mask off all or selective bits of the address so that the GSC receives all messages or multicast-group messages. The address length is programmable to be 8 or 16 bits. An address consisting of all 1s will always be received by the GSC on the C152. The address bits are always passed from the GSC to the CPU. With user software, the address can be extended beyond 16 bits, but the automatic address recognition will only work on a maximum of 16 bits. User soft- ware will have to resolve any remaining address bits.

INFO - This is the information field and contains the data that one device on the link wishes to transmit to another device. It can be of any length the user wishes but needs to be in multiples of 8 bits. This is because multiples of 8 bits are used to transfer data into or out of the GSC FIFOs. The information field is delineated from the rest of the components of the frame by the preceding address field and the following CRC. The receiver determines the position of the end of the infor- mation field by passing the bytes through a temporary storage space. When the EOF is received the bytes in temporary storage are the CRC, and the last bit received previous to the CRC consti- tute the end of the information field.

CRC - The Cyclic Redundancy Check (CRC) is an error checking algorithm commonly used in serial communications. The C152 offers two types of CRC algorithms, a 16-bit and a 32-bit. The 16-bit algorithm is normally used in the SDLC mode and will be described in the SDLC section. In CSMA/CD applications either algorithm can be used but IEEE 802.3 uses a 32-bit CRC. The

generation polynomial the C152 uses with the 32-bit CRC is:

G(X) = X32 + X26 +X23 +X22 +X16 +X12 +X11 +X10 + X8 + X7 +X5 +X4 +X2 + X +1

Kawasaki LSI USA, Inc.

Page 38 of 120

Ver. 0.9 KS152JB2

Page 37 Page 39
Image 38
Page 37 Page 39
Contents Introduction Technical Specifications Name Description Port Pin DescriptionPIN Description Pin Name Alternate FunctionRST XTAL1XTAL2 Eben ALEPsen EpsenSpecial function Registers SFR map for the cpuReset Timing Reset Values of the SFRs Sbuf Indeterminate Tmod ConfigurationsScon PconPort 0 I/O Pad Port 2 I/O Pad Port bit I/O PadsPorts 4,5 Comments ProgramPsen Epsen Fetch viaTIMER/COUNTERS Tmod Timer/Counter Mode Control RegisterTcon Timer/Counter Control Register ModeTimer/Counter in Mode Interrupts Timer/Counter 0 in ModeIE Interrupt Enable Register Priority Level Structure Egste EDMA1 Egstv EDMA0 Egsre Egsrv Pgste PDMA1 Pgstv PDMA0 Pgsre PgsrvPgsrv PX0EX0 Egsrv 2BHPT1 PDMA1EDMA1 ET1 1BHKawasaki LSI USA, Inc Ver .9 KS152JB2 ALE Psen Power Down and IdleStatus of the External Pins during Idle and Power Down Pcon Power Control Register Smod IDLLocal Serial Channel Local Serial Port Mode ControllerSerial Port Mode Mode Load Sbuf Baud Rates MHZ Timer 1 generated commonly used Baud ratesSmod Reti SINGLE-STEP OperationJNB Kawasaki LSI USA Inc Global Serial Channel Introduction11/IDLE CRC None DC JAM CRCCsma Sdlc 11/IDLEExternal clock Internal clock Control cpu Control dma Raw Receive Raw Transmit Preamble BOF Address Info CRC EOF CSMA/CD OverviewCSMA/CD Frame Format Kawasaki LSI USA, Inc Ver .9 KS152JB2 23 24 Interframe Space Collision Detection CSMA/CD Data EncodingManchester Encoding BIT Time Jitter ToleranceUnexpected 1-to-0 Transition Narrow PulsesMissing 0-to-1 Transition Response to a Detected Collision What the GSC was doing Resolution of CollisionsGSC Inactive TfifoAlgorithm BackoffDCR BKOFF= Myslot Random BackoffPrbs Tcdcnt Load Bkoff Slot Clock Myslot Deterministic Backoff Hardware Based Acknowledge Kawasaki LSI USA, Inc Ver .9 KS152JB2 Sdlc Frame Format BOF Address Control Info CRC EOFKawasaki LSI USA, Inc Ver .9 KS152JB2 BIT STUFFING/STRIPPING Data EncodingNrzi BIT Time Acknowledgement Sending Abort CharacterLine Idle Multi-Drop Network PRIMARY/SECONDARY StationsPoint-to-point Network Ring NetworkSdlc Hdlc Using a Preamble in SdlcHDLC/SDLC Comparison User Defined ProtocolsLine Discipline Planning for Network Changes and ExpansionsDMA Servicing of GSC Channels Kawasaki LSI USA, Inc Ver .9 KS152JB2 Baud Rate Initialization Test Modes External Driver InterfaceJitter Receive BIT Time Received Local Value Manchester Encoding BIT TimeReceive Sampling Rate Received Transmit WaveformsReceiver Clock Recovery CSMA/CD Clock RecoveryRcbat Crce Determining Receiver ErrorsExternal Clocking AddressingDetermining Line Discipline 2 CPU/DMA Control of the GSCCollisions and Backoff What the GSC was doing Response GSC Register Descriptions Successful Ending of Transmissions and ReceptionsGMOD84H Xtclk PL1 PL0 PL1 PL0 Length BitsKawasaki LSI USA, Inc Ver .9 KS152JB2 DCJ DCR SA5 SA4 SA3 SA2 SA1 SA0 ARB REQ Garen Xrclk Gfien IDLRcabt Crce RDN Rfne Gren Haben Kawasaki LSI USA, Inc Ver .9 KS152JB2 LNI Noack Tcdt TDN Tfnf TEN DMA Kawasaki LSI USA, Inc Ver .9 KS152JB2 DMA Operation DMA with the 80C152DMA Registers DAS IDA Alternate Cycle ModeBurst Mode SAS ISASerial Port Demand Mode External Demand ModePCH P2 SFR DMA Cycle Resume Program Execution Timing Diagrams12 OSC.PERIODS ALE Psen P1 Inst Float DMA Transfer from Internal Memory to Internal MemoryDMA Cycle Resume Program Execution 12 OSC. Periods ALE Psen Inst DMA Data OUT PCL Inst PCHDMA Cycle 12 OSC. Periods Resume Program Execution ALE Psen Hold/Hold Acknowledge Request ModeArbiter Mode Using the HOLD/HLDA Acknowledge ARB REQDmxrq ALE ARB If Hlda = ALE AEQ ALE REQInternal Logic of the Arbiter Internal Logic of the Requester DMA Arbitration Kawasaki LSI USA, Inc.oup, Inc Ver .9 KS152JB2 Kawasaki LSI USA, Inc Ver .9 KS152JB2 Kawasaki LSI USA, Inc Ver .9 KS152JB2 DMA Arbitration with Hold/Hold Ack Summary of DMA Control Bits DAS IDA SAS ISA DoneInterrupt Structure IE0 TI+RI ET1 EX1 ET0 EX0PT1 PX1 PT0 PX0 IPN1GSC Transmitter Error Conditions Transmit Error Flags Logic for Clearing TEN, Setting TDNGSC Receiver Error Conditions Glossary Kawasaki LSI USA, Inc Ver .9 KS152JB2 DCON0/1 092H,093H Xtclk PL1 PL0 Kawasaki LSI USA, Inc 102 Ver .9 KS152JB2 Kawasaki LSI USA, Inc 103 Ver .9 KS152JB2 PT1 PX1 PT0 EX0 Myslot 0F5H DCJ DCR SA5 SA4 SA3 SA2 SA1 SA0 Smod ARB REQ Garen Xrclk Gfien IDL OVR Rcabt Crce RDN Rfne Gren Haben Kawasaki LSI USA, Inc 108 Ver .9 KS152JB2 SM0 SM1 SM2 REN TB8 RB8 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0Gate Kawasaki LSI USA, Inc 111 Ver .9 KS152JB2 Data Pointer LOW PortStack Pointer DPL.7 DPL.6 DPL5 DPL.4 DPL.3 DPL.2 DPL.1 DPL.0DPH.7 DPH.6 DPH.5 DPH.4 DPH.3 DPH.2 DPH.1 DPH.0 Timer ControlData Pointer High DPHTimer 0 LSB Timer Mode ControlGate Timer Timer 1 LSBTimer 0 MSB Timer 1 MSBSerial Data Buffer Serial Port ControlSM0 SBUF.7Program Status Word RS1 RS0Accumulator ACC.7 ACC.6 ACC.5 ACC.4 ACC.3 ACC.2 ACC.1 ACC.0Kawasaki LSI USA, Inc 119 Ver .9 KS152JB2 Kawasaki LSI USA, Inc 120 Ver .9 KS152JB2
Top Page Image Contents